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Lotus Microsystems Thermal Guides

LTG devices from Lotus Microsystems are thermally conductive yet electrically isolated silicon-based thermal jumpers. These devices are designed to guide heat away from hot electronic components, such as between active devices and ground planes, without establishing an electrical connection. LTG devices significantly enhance thermal conductivity, particularly in situations with limited or no direct access to a ground plane or heatsink, such as in a high-side switch in a half-bridge configuration.Silicon, used as an alternative to traditional ceramic materials in the construction of thermal jumpers, offers a cost-effective solution with high thermal conductivity and excellent thermomechanical properties, and is reliably processed. The incorporation of LTG devices improves circuit reliability and reduces the overall cost of the thermal management system. They are available in three standard EIA sizes (0201, 0402, 0603:

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Low Latency Ethernet 100G MAC and PHY FPGA IP

Altera offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet FPGA IP core targeted to network infrastructure and data centers. The Low Latency 100G Ethernet FPGA IP core is compliant with the IEEE 802.3ba-2010 Standard. It includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional forward error correction (FEC) block.

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Low Latency Ethernet 10G MAC FPGA IP

The Low Latency Ethernet 10G MAC FPGA IP core offers low round-trip latency and efficient resource footprint. This IP core offers programmability of various features listed. It can be used in conjunction with the Multi-Rate PHY FPGA IP core to support the range of 10M/100M/1G to 10G data rates.

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Low-Latency 10G Ethernet MAC - MLE FPGA IP Core Design

The 10G Ethernet MAC IP Core from Fraunhofer Heinrich Hertz Institute is a low latency Ethernet Media Access Controller (MAC) according to IEEE802.3 -2008 specification. The IP Core was specifically designed to have the lowest possible latency, and to be as resource efficient as possible at the same time.

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LVDS Tunneling Protocol and Interface IP

LVDS Tunneling Protocol and Interface (LTPI) is a soft IP introduced in the DC-SCM 2.0 specification to facilitate the tunneling of low-speed signals between the host platform module (HPM) and secure control module (SCM) through the low-voltage differential signaling (LVDS) interfaces.

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M.2-FMC Adapter Board for NVMe SSD (AB17-M2FMC)

This adapter board converts 8 FMC high-speed differential signals (DP0–DP7) into two 4-lane PCIe® standard M.2 interfaces. It is compatible with Altera FPGA evaluation boards featuring an HPC (High Pin Count) FMC connector, allowing users to evaluate the NVMe-IP core from Design Gateway.

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M.2-PCIe Adapter Board for PCIe Gen5 SSD (AB19-M2PCI)

This adapter board converts 16-lane PCIe® interface to four 4-lane PCIe standard M.2 interfaces, supporting PCIe Gen5 speeds. This adapter can be applied to FPGA evaluation boards from Altera so that user can evaluate NVMe™ series IP Core operation and can use for prototype development platform.

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MACsec FPGA IP

The MACsec FPGA IP core is a fully configurable soft IP that implements the IEEE Media Access Control Security standard as defined in 802.1AE (2018). MACsec provides data confidentiality and integrity for the Ethernet protocol and is commonly used to secure network traffic in a variety of different applications.This IP core makes use of the Symmetric Cryptographic Accelerator (SCA) Hard IP, which is available in select Agilex 7 F-series and I-series devices. With the SCA, Altera's MACsec IP core can achieve 100 Gbps full-duplex line rates. Note that the SCA can also be used as a stand alone cryptographic accelerator.

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MAX® 10 Device Family - DE10-Lite Board

The kit provides the perfect system-level prototyping solution for industrial, automotive, consumer, and many other market applications.

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