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PTP Ordinary Clock (IEEE1588 – Precision Time Protocol)

Full standalone hardware only solution of a PTP Ordinary Clock

PTP Timestamp Unit (IEEE1588 – Precision Time Protocol)

PTP Timestamp Unit

PTP Transparent Clock (IEEE1588 – Precision Time Protocol)

Full standalone hardware only solution of a PTP Transparent Clock

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Q-Box v2

Network cybersecurity appliance designed specifically for critical infrastructure and OT systems in retrofit or greenfield deployments. Provides a quantum and AI resistant base for a Zero Trust network architecture through cryptographically enforced micro-segmentation.

Quality+ IP - 1:10 video compression preserves image SNR

Gidel’s Quality+ (Q+) IP targeting FPGA compresses Color Filter Array (CFA – e.g., Bayer), Monochrome, and RGB images and videos in real-time. Q+ revolutionizes image compression, achieving up to 1:10+ compression ratios for high-bandwidth image streams while preserving original image quality.The Quality+ IP can be embedded seamlessly in Gidel's image acquisition systems, including the Gidel frame grabbers and compact edge computers. The compression supports high-end camera streaming, including 10+ GigE Vision, CoaXPress and Camera Link. Gidel's real-time compression IPs are particularly beneficial for high-bandwidth and high-resolution imaging and vision applications enabling to improve image quality while increasing recording time, reducing storage size, and reducing post recording data offload and compression time on host computer.

QUIC Client 1Gbps IP core (QUIC1GC-IP)

QUIC (Quick UDP Internet Connections) is a modern transport layer protocol designed to overcome the limitations of TCP while providing TLS 1.3-level security. Design Gateway's fully hardware-based QUIC-IP offloads the CPU by handling TLS 1.3 handshake, payload encryption/decryption, and managing both the QUIC and UDP/IP layers. This enables secure, high-performance communication entirely through hardware logic.

QUIC Server 10Gbps IP core (QUIC10GS-IP)

QUIC (Quick UDP Internet Connections) is a modern transport layer protocol designed to overcome the limitations of TCP while providing TLS 1.3-level security. Design Gateway's fully hardware-based QUIC-IP offloads the CPU by handling TLS 1.3 handshake, payload encryption/decryption, and managing both the QUIC and UDP/IP layers. This enables secure, high-performance communication entirely through hardware logic.

R-Tile PCIe* Hard IP

R-Tile is an FPGA companion tile that supports PCI Express* configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP) and Transaction Layer (TL) Bypass modes. PCIe 3.0, 4.0, and 5.0 configurations are natively supported.

Random Access & Multi User NVMe Gen5 IP core (rmNVMe-IP)

rmNVMe-IP (Random Access & Multi-User NVMe IP) is a high-performance NVMe™ host controller optimized for high-IOPS random access applications. With pure hardware logic and no CPU involvement, it supports multiple user interfaces for simultaneous read/write access to a single NVMe SSD. Ideal for use cases like real-time sensor data fusion, OS file system offloading, and SSD testing, it offers excellent energy efficiency, performance, and low FPGA resource usage.