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JPEG-EX-S: Baseline and Extended JPEG Encoder

The JPEG-EX-S IP core supports Baseline and Extended Sequential DCT modes of ISO/IEC 10918-1, implementing a high-performance, area-efficient HW JPEG encoder for ASIC or FPGA with low latency. It produces compressed JPEG images and Motion-JPEG payloads, handling 8- or 12-bit samples and up to four components in all common subsampling formats. Processing one sample per cycle, it can compress multiple Full-HD channels even in low-cost FPGAs. One of the smallest encoders, it uses ~80k gates in ASICs. Once programmed, it operates standalone without host assistance. Integration is simple via AMBA®: AXI Streaming for pixels/data and 32-bit APB for registers, with optional AXI Streaming for timestamps or metadata. CAST offers IP Integration Services delivering complete JPEG subsystems with decoders, video interfaces, UDP/IP or Transport Stream stacks, or other IP. Designed to industry best practices, reliability is proven by verification, production use, and a bit-accurate software model.

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JPEG-LS-D: Lossless & Near-Lossless JPEG-LS Decoder

The JPEG-LS-D core, a highly efficient & low-power, lossless & near-lossless image decompression engine & compliant to the JPEG-LS, ISO/IEC 14495-1 standard, can decompress any JPEG-LS stream or JPEG-LS payload of image container formats. It accepts compressed streams of images with up to 16-bit per color samples & up to 4 color components, in all widely used color subsampling formats, supporting oversize image dimension parameters & resolutions higher than 64k x 64k. With standalone operation, parsing marker segments & decompressing coded data, the core reports back the image format. APP or COM marker segments are also passed to the system via a dedicated interface. Straightforard integration, standardized AMBA® I/F (compressed data & outputs pixel data, frame format information, APP or COM marker via AXI4-Stream - access to control & status registers via 32-bit APB). A wrapper that bridges the AXI-Stream interfaces to AXI4 can optionally be delivered with the core.

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JPEG-LS-E: Lossless & Near-Lossless JPEG-LS Encoder

The JPEG-LS-E core is a low-power, high-efficient image compression engine compliant with JPEG-LS (ISO/IEC 14495-1). Based on the LOCO-I algorithm, it achieves compression ratios comparable or superior to JPEG2000 in lossless mode, while requiring far less area & memory thanks to its low complexity & line-based processing. Its Near-Lossless mode enables higher compression ratios with visually lossless quality, letting users define the max pixel error. It delivers full JPEG-LS compression efficiency in a compact, easy-to-integrate hardware block. It connects through AMBA® interfaces: AXI4-Stream for image input & compressed output, & a 32-bit APB for control & status. Once configured, it can process unlimited images without host intervention, with optional metadata or timestamps inserted via a dedicated streaming port. The core’s robustness has been proven through extensive verification & silicon validation & is delivered with a full verification environment & bit-accurate SW model.

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LDPC for eMMC (Silicon Proven IP for Altera Devices)

Mobiveil’s LDPC for eMMC offers robust error correction and flash endurance in a compact, low-power footprint. It is tailored for smartphones, tablets, and enterprise SSDs requiring scalable, high-reliability flash storage. The IP meets performance needs while extending memory life significantly.

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LDPC for Flash Controller (Silicon Proven IP for Altera Devices)

Mobiveil’s LDPC Controller offers advanced LDPC error correction with statistical DSP. It addresses the reliability demands of MLC, TLC, and 3D NAND at advanced geometries while significantly extending flash memory life. Optimized for ultra-low power to high-performance SSD applications, it is scalable, patented, and highly customizable.

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LIN: LIN Bus Master/Slave Controller

The LIN-CTRL core is a controller that transmits and receives complete LIN frames to perform serial communication according to the LIN Protocol Specification. It can be configured before the synthesis to operate as a master, slave or include both profiles. When configured with both – master and slave, then at run-time, the LIN-CTRL can operate either as a master or as a slave and supports versions 1.3, 2.0, 2.1, and 2.2 of the LIN protocol. The message transfers can be controlled via a microcontroller interface and a LIN transceiver is needed for the connection to the LIN bus. The LIN-CTRL core is a microcode-free design developed for reuse in ASIC and FPGA implementations. The robustly verified core has been production-proven multiple times. The LIN controller core is available in two versions: Standard, and Safety-Enhanced. The Safety-Enhanced versions are certified as ISO-26262 ASIL-D Ready.

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Lossless Compression IP

Gidel’s lossless compression IP targeting FPGA performs real-time compression for Color Filter Array (CFA – e.g., Bayer), Monochrome, and RGB images and videos. The IP enables compression of multi-camera/sensor inputs at pixel clock rates exceeding 1 gigapixel/s while using very small FPGA resources and minimal power consumption. The compression is highly efficient and, in real-case video applications, has achieved a lossless compression ratio of 1:2.3. The Lossless IP can be embedded seamlessly in Gidel's image acquisition systems, including the Gidel frame grabbers and compact edge computers. The compression supports high-end camera streaming, including 10+ GigE Vision, CoaXPress and Camera Link. Gidel's real-time compression IPs are particularly beneficial for high-bandwidth and high-resolution imaging and vision application enabling increased recording time, reduced storage size, and reduced post recording data offload and compression time on host computer.

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Low Latency Ethernet 100G MAC and PHY FPGA IP

Altera offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet FPGA IP core targeted to network infrastructure and data centers. The Low Latency 100G Ethernet FPGA IP core is compliant with the IEEE 802.3ba-2010 Standard. It includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional forward error correction (FEC) block.

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Low Latency Ethernet 10G MAC FPGA IP

The Low Latency Ethernet 10G MAC FPGA IP core offers low round-trip latency and efficient resource footprint. This IP core offers programmability of various features listed. It can be used in conjunction with the Multi-Rate PHY FPGA IP core to support the range of 10M/100M/1G to 10G data rates.

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