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The Creonic AWGN Channel IP core is a noise generator capable of processing up to a maximum of 512 symbols in parallel.
By Creonic GmbH
The Creonic Polar Encoder IP core is a scalable solution featuring code-rate flexibility, high throughput and very low latency on state-of-the-art FPGAs.
The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GMR Release 2 (GMPRS-1) and use LDPC codes for the first time.
The Creonic WiGig LDPC decoder is designed in particular to deliver highest throughputs in the multi-gigabit domain with a small footprint.
The Creonic IEEE 802.11 LDPC decoder is a high performance implementation for WLAN and further applications and supports all LDPC codes as defined by the standard.
The Creonic IEEE 802.15.3c LDPC Decoder IP supports all LDPC codes with a codeword size of 672 bits as defined by the standard.
The Creonic ITU 25G PON LDPC Encoder and Decoder support the default LDPC (17280, 14592) coding scheme, as well as the optional LDPC (17152, 14592) scheme. The
The Creonic MMSE detector IP core offers high throughputs even on low-cost FPGAs
The Creonic NCR Processor IP core has two main functionalities: NCR tracker and NCR local clock