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Creonic SDA OCT V 3.0 Encoder and Decoder

The Creonic SDA OCT V3.0 Encoder handles the construction of Over-The-Air (OTA) frames as indicated in the standard, a preamble followed by a header and payload data, with both fields being protected by cyclic redundancy check (CRC) and forward error correction (FEC).

By Creonic GmbH

Creonic Ultrafast BCH Decoder

The Creonic Ultrafast BCH Decoder is capable of processing an entire BCH codeword per clock cycle in a pipelined way. Therefore, it achieves outstanding data rates.

By Creonic GmbH

Creonic Wideband DDC Digital Down Converter

The Creonic Wideband Digital Down Converter (DDC) digitally converts the input signal at IF frequency down to baseband by multiplying input samples with sine/cosine waves generated by numerical controlled oscillators (NCO).

By Creonic GmbH

Creonic WiMedia 1.5 LDPC Encoder/Decoder

The solution from Creonic for data rates of up to 1 Gbit/s offers outstanding efficiency in terms of implementation complexity.

By Creonic GmbH

Cryptographic Accelerator

Eideticom’s Cryptographic Accelerator is a security platform designed to accelerate public key cryptography in datacenter environments. It supports both classical and post-quantum cryptographic (PQC) algorithms and is built to help cloud service providers (CSPs) and content delivery networks (CDNs) transition to PQC while maintaining performance and security. Our Cryptographic Accelerator ensures secure key management while significantly enhancing overall system performance. Eideticom’s Cryptographic Accelerator utilizes ML-KEM (FIPS 203) and ML-DSA (FIPS 204), ensuring support for NIST-approved post-quantum cryptographic standards.

By Eideticom

CSENT-Rx: SENT/SAE J2716 Receiver

The CSENT-RX core implements a receiver for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and supports both synchronous and asynchronous sensors. It can be used for receiving data from one or multiple sensors using a single SENT line. The CSENT-RX provides access to its control, status, and data registers via a 32-bit APB, or AXI4-Lite bus interface. The core provides a glitch filter on the serial data input and has data mapping functionality on received data to offload the connected host from data formatting. The received data are accessible via the register interface. The core is also capable of generating trigger pulses requesting synchronous sensors to send data. A set of handshaking signals facilitates the integration with an external DMA controller. The CSENT-RX core is designed with industry best practice, has been rigorously verified and is production proven.

By Computer Aided Software Technologies, Inc (dba CAST)

CTAccel Image Processing (CIP) Accelerator

By CTAccel Limited

Current: xSPI Initiator core.  

xSPI Memory Controller Core for PSRAM, NOR Flash, STT-MRAM. Protocols: (a) JEDEC xSPI Profile 1.0, 2.0; (b) HyperBus 1.0, 2.0, 3.0; (c) OctaBus; (d) Octal Bus; (e) Exccela Bus. SLL support x8 and x16 PSRAM devices, and support chaining two x16 PSRAM devices to create x32 PSRAM channel.

By Synaptic Laboratories Ltd

Custom Development: from Requirements over Specification, Design, Architecture Implementation and Verification to Deployment.

NetTimeLogic provides design services in the areas of FPGA and embedded software development, especially in the areas of time synchronization and network redundancy. From requirements engineering over custom IP core development, OS porting, drivers, GUIs and testing to education and consulting, we can help you to bring your system to a success. We develop FPGA firmware in VHDL and Verilog. From simple entities to complete IP core solution we can help you in every step of FPGA development

By NetTimeLogic GmbH