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DVB-CID Modulator

The CMS0069 DVB-CID modulator is an integrated modulator and channel-coder core designed specifically to address the requirements of the ETSI DVB-CID carrier identification standard (EN103129).

DVB-RCS2 Modulator

The IP core performs all tasks of the inner transmitter and complements the Creonic DVB-RCS2 receiver solutions.

DVB-RCS2 Multi-Carrier Receiver

The Creonic DVB-RCS2 Multi-Carrier Receiver IP core supports multiple frequency time domain multiple access (MF-TDMA), performs all tasks of a DVB-RCS2 receiver including carrier separation, baseband conversion, demodulation, and turbo decoding.

DVB-S / DVB-DSNG Demodulator

The CMS0048 has been designed from the ground-up for high-speed and gate-efficient implementation on FPGA and ASIC platforms and offers very high performance when combined with either the integrated FEC decoder or an external advanced FEC decoder. The demodulator provides an adaptable starting point for receiver sub-systems to be used in both the current and next-generation of digital TV set-top-boxes

DVB-S / DVB-DSNG Modulator

The CMS0010 DVB-S modulator / DSNG modulator is an integrated modulator and Reed-Solomon encoder core designed specifically to address the requirements of the ETSI DVB-S forward-link satellite Standard (EN300421).

DVB-S2 / DVB-S2X Modulator

DVB-S2 / DVB-S2X Modulator with integrated FEC encoder

DVB-S2 demodulator / S2X demodulator

DVB-S2X Demodulator

DVB-S2 IP

The DVB-S2 (Digital Video Broadcasting - Satellite - Second Generation) IP Core offers a high-performance, fully compliant, and cost-efficient solution for satellite-based communication systems. Designed to implement the ETSI EN 302 307 standard, our DVB-S2 IP Core supports all key features of the specification, including powerful LDPC/BCH Forward Error Correction, adaptive coding and modulation (ACM), and multi-stream transmission—enabling robust and bandwidth-efficient data transmission over satellite links.

DVB-S2X LDPC/BCH Decoder

The Creonic DVB-S2X decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 100 MSymbols/s on state-of-the-art FPGAs.