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HSR & PRP Network Redundancy (IEC62439-3)

Full standalone hardware only solution of a HSR & PRP Network Redundancy Dual Attached Node (DAN) and RedBox

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HyperBus Controller (Silicon Proven IP for Altera Devices)

Mobiveil’s HyperBus Controller enables high-speed (up to 333 MB/s) flash access over a 12-pin interface, surpassing legacy SPI/QSPI protocols. It supports AXI interface, 0-wait-state writes, continuous burst reads, and XiP execution. Ideal for HyperFlash/HyperRAM integration, it maximizes throughput and performance in constrained systems.

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HyperRAM Controller (Silicon Proven IP for Altera Devices)

The HyperRAM Controller supports Winbond’s HyperBus-based HyperRAM devices used in IoT, automotive, and industrial SoCs. Written in tech-agnostic Verilog RTL, it supports major simulation and synthesis tools. The controller ensures seamless memory integration with minimal resource usage.

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I2C-SMBUS

The I2C-SMBUS core is a serial interface controller for the Inter-Integrated Circuit (I2C) and System Management Bus (SMBus), and is also suitable for the Power Management Bus (PMBus). It can operate as a bus master or slave, with simple programming and easy integration. An arbitration mechanism enables use in multi-master systems, while SMBus clock synchronization supports fast-master/slow-slave communication. The core prevents deadlocks by detecting timeouts and errors and includes glitch filtering on the serial line. Control, status, and data registers are accessible via AMBA APB or a generic memory-mapped interface. Designed for reuse in ASIC and FPGA implementations, it is microcode-free and uses only rising-edge-triggered flip-flops with configurable reset types. The design avoids tri-states, ensuring straightforward scan insertion and efficient implementation in embedded systems.

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I2S-TDM: I2S/TDM Multichannel Audio Transceiver

The I2S-TDM IP core is a configurable, full-duplex, multi-channel serial audio transceiver supporting both Inter-IC Sound (I2S) and Time-Division Multiplexed (TDM) interfaces. It can operate as either controller (master) or target (slave), exchanging audio samples over programmable serial lines. Designers can configure parameters such as sample width (2–32 bits), sample rate, frame format, number of channels, and allocation per line at run time, while synthesis-time options define maximum supported channels and lines. Integration is simplified with APB or AXI4-Lite control interfaces and AXI4-Stream for audio data, with clean clock domain crossings. The core is delivered as Verilog RTL or FPGA netlist, with testbench, scripts, drivers, and documentation, and typically uses about 10K gates for an 8-channel configuration.

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I3C-SC: MIPI I3C Basic Secondary Controller

The I3C-SC core is a versatile MIPI® I3C Secondary Controller compliant with the latest I3C BasicSM specification. It can operate as a bus controller or target, supporting SDR communication while tolerating HDR traffic, and coexisting with legacy I2C devices. As a target, it autonomously handles Common Command Codes (CCCs), supports dynamic or static addressing, Hot-Join, and In-Band Interrupts. The core offers two operating modes: normal mode, where data is exchanged via an APB subordinate interface, and I3C-to-AHB bridging mode, where private I3C/I2C transfers are converted into AHB transactions for remote monitoring, configuration, or data exchange without software intervention. Flexible synthesis-time and run-time options allow customization of features, size, and behavior. With industry-best design practices, clean clock domain crossings, and FPGA validation, the I3C-SC ensures reliable, low-risk integration into ASIC or FPGA designs.

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I3C-T: MIPI I3C Basic Target

The I3C-T core is a flexible, target-only MIPI® I3C controller compliant with the latest I3C-BasicSM specification. Supporting SDR communication while tolerating HDR traffic, it interoperates with legacy I2C devices and can optionally function as an I2C target. The core autonomously handles relevant Common Command Codes (CCCs), supports dynamic or static addressing, Hot-Join, and In-Band Interrupts. It offers two operating modes: normal mode, where data transfers use an APB subordinate interface, and I3C-to-AHB bridging mode, where private I3C/I2C transactions are automatically converted into AHB accesses for remote monitoring, configuration, debug, or data exchange without software intervention. With both synthesis-time and run-time configurability, the I3C-T adapts to application needs while minimizing footprint. Designed with best coding practices, clean clock domain crossings, and FPGA validation, it ensures reliable, low-risk integration.

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IA-220-U2 Computational Storage Processor

M.2 FPGA module with PCIe Gen4

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IA-420f PCIe Agilex™ 7 F-Series FPGA Card 

HHHL PCIe FPGA card with 200G, and up to 16 GB DDR4

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Showing 343-351 of 664 Offerings