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Company Name

By Source

Altera Solutions
Partner Solutions

Offering Types

Acceleration / AI / Cloud
- Artificial Intelligence (AI)
- Data Processing / Analysis / Acquisition
- Data Science
- Edge
- Machine Learning
- Neural Network
- Public / On Premise
- Regional / District / Central
- Storage / Compression
Boards / SOMs / Dev Kits
- COTS
- Daughter Card
- Development / Evaluation Kit
- DPU / IPU / AI NIC / SmartNIC
- PCI Express
- System-on-Module (SOM)
- VPX
Design Services
- Board Level Design (DS)
- Certification (DS)
- Custom IP (DS)
- Debug (DS)
- Design for Manufacturing (DS)
- FPGA Design (DS)
- Logistics (DS)
- Manufacturing (DS)
- Schematic / Layout Review & DFT (DS)
- SI / PI Simulation (DS)
- Software (DS)
- System Level Design (DS)
- Verification / Validation (DS)
EDA Tools / IDE
- Design
- Embedded Tools
- Protocol Analysis
- Simulation
- Verification
Education / Training
- Acceleration / Artificial Intelligence (AI)
- Design Optimization
- Digital Signal Processing
- Embedded Processing
- External Memory Interfaces
- HDL Design Methodologies
- Interface Protocols
- Quartus Design Flow
- Security
Intellectual Property (IP)
- Digital Signal Processing / AI
  - Artificial Intelligence
  - Error Correction
  - Filters /Transforms
  - Floating Point
  - Modulation
  - Video and Image Processing
- Interfaces
  - Audio / Video
  - Communication
  - Compute Express Link (CXL)
  - Ethernet
  - High Speed
  - Networking / Security
  - PCI Express (IP)
  - Serial
- Memory Controllers
  - DMA
  - Flash
  - SDRAM
  - SRAM
- Soft Embedded Processors
  - RISC V
- Transceivers & Basic Functions
  - Clocks, PLLs and Resets
  - Simulation, Debug and Verification
  - Transceivers
Manufacturer
- Board Level Design (MF)
- Certification (MF)
- Custom IP (MF)
- Debug (MF)
- Design for Manufacturing (MF)
- FPGA Design (MF)
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- Schematic / Layout Review & DFT (MF)
- SI / PI Simulation (MF)
- Software (MF)
- System Level Design (MF)
- Verification / Validation (MF)
Software / OS / RTOS
- Drivers
- Embedded
- Operating System (OS)
- Real Time Operating System (RTOS)
System Integrator / Provider
- Board Integration
- Chassis construction
- Chip Integration
- Software Integration

Region

Americas
Asia Pacific
Europe & Middle East
Japan
People’s Republic of China

Device Family

Agilex™ 3 FPGA C-Series
Agilex™ 5 FPGA D-Series
Agilex™ 5 FPGA E-Series
Agilex™ 7 FPGA F-Series
Agilex™ 7 FPGA I-Series
Agilex™ 7 FPGA M-Series
Agilex™ 9 FPGA Direct RF-Series
Arria® 10 Bare Die
Arria® 10 GT FPGA
Arria® 10 GX FPGA
Arria® 10 SX FPGA
Arria® II GX FPGA
Arria® II GZ FPGA
Arria® V GT FPGA
Arria® V GX FPGA
Arria® V GZ FPGA
Arria® V ST FPGA
Arria® V ST SoC FPGA
Arria® V SX FPGA
Arria® V SX SoC FPGA
Cyclone® 10 GX FPGA
Cyclone® 10 LP FPGA
Cyclone® II FPGA
Cyclone® III Bare Die
Cyclone® III FPGA
Cyclone® III LS FPGA
Cyclone® IV E FPGA
Cyclone® IV GX FPGA
Cyclone® V E FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Cyclone® V SE FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX FPGA
Cyclone® V SX SoC FPGA
eASIC™ N3X Devices
eASIC™ N3XS Devices
eASIC™ N5X Devices
Agilex® 3 FPGAs and SoC FPGAs C-Series
Agilex® 5 FPGAs and SoC FPGAs D-Series
Agilex® 5 FPGAs and SoC FPGAs E-Series
Agilex® 7 FPGAs and SoC FPGAs F-Series
Agilex® 7 FPGAs and SoC FPGAs I-Series
Agilex® 7 FPGAs and SoC FPGAs M-Series
Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series
Arria® 10 GT FPGA
Arria® 10 GX FPGA
Arria® 10 SX SoC FPGA
Cyclone® 10 GX FPGA
Cyclone® 10 LP FPGA
eASIC® N3X Devices
eASIC® N3XS Devices
eASIC™ N3X Devices
eASIC™ N3XS Devices
MAX® 10 FPGA
Stratix® 10 AX SoC FPGA
Stratix® 10 DX FPGA
Stratix® 10 GX FPGA
Stratix® 10 SX SoC FPGA
Stratix® 10 TX FPGA
MAX® 10 FPGA
MAX® II CPLD
MAX® II Z CPLD
MAX® V CPLD
Mustang Mesa
Stratix® 10 AX FPGA
Stratix® 10 Bare Die
Stratix® 10 DX FPGA
Stratix® 10 GX FPGA
Stratix® 10 SX FPGA
Stratix® 10 TX FPGA
Stratix® III FPGA
Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GX FPGA

Market Segments

Access
- Cable Access
- Carrier Access
- Other Access
Aerospace
- Aerospace
ASIC Proto
- ASIC Emulation
- ASIC Prototyping
Broadcast
- Broadcast Studio
- ProAV
Consumer
- Gaming
- Home Audio/Video
- Multi-Functional Printer
- Other Consumer
Defense
- MIL COMMS
- Radar/Ew
Industrial
- Energy
- Industrial / Manufacturing
- Robotics
- Vision
Government
- Chassis construction
- Drivers
- Govt Infrastructure
- Other ADG
- Software Integration
Medical
- Imaging
- Lab/Life Sciences
- Non-Imaging Patient Devices
- Other Medical
- Ultrasound
- Video
Data Center OEM (IHV, ISV, SI, VAR)
- AI/HPC
- CDNs
- IaaS/PaaS
- Networking
- Storage
- Transmission
Transportation
- Automotive (Passenger Vehicles)
- Non-Automotive Transportation
- Charging Infrastructure
- Transportation Infrastructure (non-charging)
Data Center Cloud (Public, Private, Hybrid)
- AI/HPC
- IaaS/PaaS
- Networking
- CDNs
- Storage
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Wireless
- Baseband
- AI-RAN
- NTN/Fixed Wireless
- DAS/repeater/RIS
- xhaul Hub
- RDU
- FWA/backhaul
- 5G/ 6G Radio
Test
- ATE
- RF Instrumentation
- Communication Tester
- Other Test

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ISDB-S3 modulator

The CMS0070 ISDB-S3 (A)PSK modulator is an integrated modulator and channel-coder core designed specifically to address the requirements of the ARIB STD-B44 advanced wide-band digital satellite broadcasting Standard.

By Commsonic Ltd

View Details

ISDB-T Modulator

The ISDB-T modulator / ISDB-TB modulator core enables rapid development of audio and visual systems using commodity free-to-air set-top-box products.

By Commsonic Ltd

View Details

Jedec xSPI Controller (Silicon Proven IP for Altera Devices)

Mobiveil’s xSPI Controller supports JEDEC-compliant NOR/NAND Flash and HyperRAM devices, enabling ultra-fast read throughput via x4/x8 SPI interfaces. It functions as a universal controller—SPI, Quad-SPI, Octa-SPI, or Dual-QSPI—ensuring backward compatibility with legacy devices. Designed for space-constrained, low-power applications, it supports multiple chip-selects and is ideal for wearables, cameras, and automation systems.

By Mobiveil Inc.

View Details

JESD204 FPGA IP

Altera JESD204 IP is a high-performance, JEDEC-compliant interface solution designed to simplify and accelerate the integration of high-speed data converters with digital processing systems. Supporting data rates up to 32.44 Gbps, it efficiently manages the physical, data link, and transport layers while offering pre-verified design examples and intuitive configuration, significantly reducing development time. Its robust clock synchronization and interoperability features ensure reliable, standards-based performance across demanding applications.

By Altera

View Details

JESD204B TRANSMITTER AND RECEIVER IP

Logic Fruit's JESD204B RTL IP supports increased lane rates up to 12.5Gbps for higher bandwidth applications. It can be configured to transmit or receive using a 8B10B link layer to achieve deterministic latency, SerDes synchronization, clock recovery and DC balance.

By Logic Fruit Global Technologies Inc

View Details

JESD204C TRANSMITTER AND RECEIVER IP

Logic Fruit's JESD204C RTL IP supports increased lane rates upto 32Gbps for higher bandwidth applications. This IP can be configured to transmit or receive using either a 64B66B or 8B10B link layer with improved efficiency of payload delivery, and also provides for an improved robustness of the link with a backward-compatible option to JESD204B.

By Logic Fruit Global Technologies Inc

View Details

JPEG-D-S: Baseline JPEG Decoder

The JPEG-D-S IP core is a compact, high-performance hardware JPEG decoder supporting the Baseline Sequential DCT mode of ISO/IEC 10918-1. It decompresses JPEG images and Motion-JPEG payloads, handling 8-bit samples and up to 4 components in all common subsampling formats. Processing 1 sample/cycle, it can decode multiple Full-HD channels even in cost-sensitive FPGAs. One of the smallest decoders, it uses about 4,000 ALMs in Altera FPGAs. Once programmed, it operates standalone, parsing markers and decompressing without host intervention. It reports resolution, subsampling, and depth for proper post-processing or display. Integration is simple via AMBA®: AXI Streaming for pixels/data and a 32-bit APB slave for registers. CAST offers integration services delivering complete JPEG subsystems with decoders, video interfaces, networking stacks, or other IP. Designed with best practices, its proven reliability is backed by verification, production use, and a bit-accurate software model.

By Computer Aided Software Technologies, Inc (dba CAST)

View Details

JPEG-DX-F: Ultra-Fast Baseline and Extended JPEG Decoder

This JPEG decompression IP core supports the Baseline & Extended Sequential DCT modes of the ISO/IEC 10918-1. It is scalable and ultra-high-performance, while handles extremely high pixel rates of JPEG images and video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. It can process from 2 to 32 color samples per clock cycle. Paired with the JPEG-EX-F Encoder Core provide an extremely cost-effective solution. Standalone operation, once programmed, parsing marker segments, decompressing coded data and reporting back the image format. SoC integration is straightforward (standard AMBA I/F - AXI Streaming & APB Slave). CAST’s IP Integration Services are also available for JPEG subsystems (the JPEG decoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST).

By Computer Aided Software Technologies, Inc (dba CAST)

View Details

JPEG-DX-S: Baseline and Extended JPEG Decoder

The JPEG-DX-S IP core is an area-efficient high-performance JPEG decoder supporting Baseline and Extended Sequential DCT modes of ISO/IEC 10918-1. It decodes JPEG and Motion-JPEG payloads, supporting 8- or 12-bit samples and up to four components in standard subsampling formats. Processing one sample per cycle, it can handle multiple Full-HD channels in cost-sensitive FPGAs. One of the smallest available, it requires ~76k gates in ASICs. Once configured, the core runs standalone, parsing markers and decompressing without host intervention. It reports resolution, subsampling, and depth for correct post-processing. Integration is simple via AMBA®: AXI-Stream for pixels/data and a 32-bit APB for registers. CAST offers integration services delivering complete JPEG subsystems (decoders, video interfaces, networking stacks, etc.). Designed to industry best practices, quality is proven by verification, silicon validation, and a bit-accurate software model. Scan-ready, LINT-clean, production.

By Computer Aided Software Technologies, Inc (dba CAST)

View Details

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ISDB-S3 modulator

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JPEG-D-S: Baseline JPEG Decoder

JPEG-DX-F: Ultra-Fast Baseline and Extended JPEG Decoder

JPEG-DX-S: Baseline and Extended JPEG Decoder

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ISDB-S3 modulator

ISDB-T Modulator

Jedec xSPI Controller (Silicon Proven IP for Altera Devices)

JESD204 FPGA IP

JESD204B TRANSMITTER AND RECEIVER IP

JESD204C TRANSMITTER AND RECEIVER IP

JPEG-D-S: Baseline JPEG Decoder

JPEG-DX-F: Ultra-Fast Baseline and Extended JPEG Decoder

JPEG-DX-S: Baseline and Extended JPEG Decoder