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AES 256 GCM 10G25G IP for Networking Applications

AES256-GCM-10G25G IP core implements the advanced encryption standard (AES) with 256-bit key in Galois/Counter Mode (GCM) which is widely used for Authenticated Encryption with Associated Data (AEAD) application. This IP core can achieve high throughput 38.4 Gbps @300MHz, suitable to work together with our TOE10G and TOE25G IP core for high performance and secure communication applications.

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AES 256 IP

AES-256 IP supports ECB mode for both encryption and decryption, processing 128-bit data blocks in a constant 15 clock cycles. It delivers 8.53 Mbps per MHz, achieving up to 3.41 Gbps at 400 MHz. Designed to enhance the security of data storage and networking IP cores, it enables secure, efficient, and high-performance applications.

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AES 256 XTS IP

Design Gateway’s AES-256 XTS IP core is a high-performance, hardware-only encryption engine designed for secure data protection in storage applications. The IP implements the AES algorithm in XTS (XEX-based Tweaked-codeBook mode with ciphertext Stealing) mode, which is widely used for disk encryption standards, including for SSDs and secure storage devices. Operating without the need for a CPU or software, the IP core provides real-time encryption and decryption with minimal latency, making it ideal for security-critical systems. Optimized for Altera FPGA platforms, the AES-256 XTS IP core supports 256-bit key sizes and delivers reliable and efficient encryption throughput that scales with your system’s clock and data interface configuration. It is an excellent choice for applications in defense, medical imaging, financial systems, and any domain requiring secure, high-speed data storage. Easy integration with existing Design Gateway IP cores, such as NVMe-IP or SATA-IP, allows for sea

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AES 256 XTS STG 2X IP for NVMe Gen4

As storage performance continues to accelerate, the need for high-speed, real-time data encryption has become a critical challenge. To meet this demand, Design Gateway’s AES-XTS IP core is optimized for NVMe PCIe Gen4 SSDs, delivering advanced data protection without compromising system speed or efficiency. Built entirely in hardware logic, this IP core accelerates encryption and decryption processes, ensuring minimal latency and maximum throughput. It enables seamless integration into ultra-high-speed storage systems while maintaining robust data security—making it ideal for enterprise storage, secure recording, and high-performance computing environments. With support for real-time processing at PCIe Gen4 speeds, the AES-XTS IP core is a powerful solution for organizations looking to protect sensitive data while leveraging the full potential of next-generation NVMe storage.

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AES 256 XTS STG 4X IP for NVMe Gen5

As PCI Express Gen5 technology becomes the backbone of next-generation storage, the need for real-time data protection is more critical than ever. Design Gateway’s AES-XTS-STG-4x IP core delivers robust, high-speed encryption for NVMe SSDs, providing seamless real-time protection without compromising performance. Designed specifically for PCIe Gen5 environments, this IP core supports full-bandwidth encryption and decryption at speeds up to 25.6 GB/s, making it ideal for securing high-throughput data storage. Built on FPGA architecture, the AES-XTS-STG-4x IP core ensures low-latency, hardware-level encryption for mission-critical applications in data centers, enterprise storage, and secure recording systems. By encrypting data before it is written to NVMe SSDs, this solution safeguards sensitive information while maintaining the speed, efficiency, and reliability demanded by high-performance storage systems.

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AES 256 XTS STG IP for NVMe Gen3

As storage performance continues to accelerate, the need for high-speed, real-time data encryption has become a critical challenge. To meet this demand, Design Gateway’s AES-XTS IP core is optimized for NVMe PCIe Gen3 SSDs, delivering advanced data protection without compromising system speed or efficiency. Built entirely in hardware logic, this IP core accelerates encryption and decryption processes, ensuring minimal latency and maximum throughput. It enables seamless integration into ultra-high-speed storage systems while maintaining robust data security—making it ideal for enterprise storage, secure recording, and high-performance computing environments. With support for real-time processing at PCIe Gen3 speeds, the AES-XTS IP core is a powerful solution for organizations looking to protect sensitive data while leveraging the full potential of next-generation NVMe storage.

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AES-CCM: Authenticated Encrypt/Decrypt Engine

The AES-CCM IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-CCM-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-CCM-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. CCM stands for Counter with CBC-MAC mode. CCM is a generic authenticate-and-encrypt block cipher mode. CBC-MAC is utilized to generate an authentication string while CTR mode is used to encrypt. The AES-CCM core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

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AES-GCM: Authenticated Encrypt/Decrypt Engine

The AES-GCM IP core implements NIST Advanced Encryption Standard (AES) in Galois Counter Mode (GCM). GCM is an authenticate-and-encrypt block cipher mode where a Galois Field (GF) multiplier/accumulator is utilized to generate an authentication tag while CTR (Counter) mode is used to encrypt. The core processes 128-bit blocks and is programmable for 128-, 192-, and 256-bit keys. Four architectural versions are available to suit system requirements. The Standard version (AES-GCM-S), more compact using a 32-bit datapath, requires 44/52/60 clocks for each data block (128/192/256-bit key, respectively). The Fast version (AES-GCM-F) achieves higher throughput using a 128-bit datapath and requires 11/13/15 clocks for each data block depending on key size. For high-throughput applications there are two additional versions. The High Throughput AES-GCM-X can process 128 bits/cycle and the Higher Throughput AES-GCM-X2 can process 256 bits/cycle respectively independent of the key size.

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AES-P: Programmable Advanced Encryption Standard Engine

The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-P-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-P-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. It can be programmed to use any of the following cipher modes: CBC, CTR, ECB, and OFB. The core works with a pre-expanded key, or with optional key expansion logic. The AES-P core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

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Showing 46-54 of 664 Offerings