banner

Find Offerings

Switch to Partners

By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by
By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by

O-RAN FPGA IP

Altera O-RAN IP delivers a flexible, standards-compliant fronthaul interface for 5G and LTE systems using the 7-2x functional split. Supporting both control and user planes per O-RAN-FH.CUS.0-v03.00, it simplifies DU-RU integration, accelerates development, and ensures interoperability in disaggregated, open RAN architectures.

OFDM Modem

The OFDM Modem IP Core is a high-performance solution for wireless and broadband systems like 5G, Wi-Fi, LTE, satellite, and tactical radios. It offers full PHY baseband functionality with support for adaptive modulation, channel estimation, and configurable IFFT/FFT sizes. Optimized for low-latency and robust performance, it’s ideal for both fixed and mobile applications.

Offering Name

Short Offering Description

ONE AI

ONE AI is a powerful framework for automatically generating optimized AI models tailored to specific applications and hardware. It enables high-performance AI on even the smallest edge devices by reducing resource requirements by up to 1000x. This allows teams across industries to deploy faster, more accurate, and cost-effective AI solutions with minimal effort.

Offerings Image

ONE WARE Studio

The Next Generation IDE for FPGA Electronics Development, to build highest efficient AI solutions & applications.

P-Tile PCIe* Hard IP

P-Tile is an FPGA companion tile that supports PCI Express* configurations up to PCIe 4.0 x16 in Endpoint (EP), Root Port (RP) and Transaction Layer (TL) Bypass modes. PCIe 3.0 and 4.0 configurations are natively supported.

Offerings Image

Parretto DisplayPort IP Core

The Parretto DisplayPort is a resource optimized DisplayPort v1.4 IP Core solution for FPGA devices. Designed for easy of use, the core is available as both source (DPTX) and sink (DPRX).

PCI-M32: 32-bit, 33 MHz PCI Master/Target

The PCI-M32 implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz PCI clock.

PCI-M32MF 32-bit/33MHz Multi-Function PCI Master/Target

The PCI-M32MF is a PCI 2.3-compliant master/target core supporting a 32-bit address/data bus at up to 33 MHz. It enables 1 to 8 independent PCI functions per chip, each with 64–256 bytes of Configuration Space and up to six Base Address Registers, supporting I/O and Memory decoding from 16 bytes to 4 GB. Backed by over 20 years of CAST PCI IP expertise, the core is designed for easy reuse and integration, and is available as synthesizable RTL or FPGA netlist with comprehensive deliverables.