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PCIe GEN6 Controller IP

The PCIe Gen 6 Controller IP supports the full PCI Express 6.x specification, offering scalable, high-speed communication for enterprise-grade solutions. FIRST in the industry to deliver PCIe IPs across multiple generations. It is: - Optimized for existing and emerging FPGA uses cases for hardening onto ASIC / SoC. - Best for large memory, compute-intensive and high data rate applications.

PCIe GEN6 PHY IP

Logic Fruit's PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for high-speed data transfer. It supports advanced applications, including AI/ML, High-Performance Computing, and next-generation storage solutions.

PCIe to SD/MMC Bridge

iWave’s PCIe to SD/MMC Bridge IP Core enables high-speed communication between PCIe hosts and SD/MMC memory cards, supporting Gen1/Gen2 PCIe. With built-in DMA and AXI interface compatibility, the core ensures reliable and efficient data storage for embedded and FPGA-based systems.

PCIe to SRIO Bridge Controller (FPGA IP for Altera Devices)

This Gen3 PCIe to SRIO Bridge enables full-speed protocol conversion with advanced messaging and DMA engines. Supporting aerospace, telecom, defense, and HPC, it ensures low-power, compact implementation. Ideal for embedded systems, it bridges PCIe versatility with SRIO performance.

PCIe x16 Lanes Crossover adapter board for NVMe SSD (AB18-PCIeX16)

The AB18-PCIeX16 adapter board supports PCIe Gen4, making it ideal for use with high-speed NVMe Gen4 SSDs. It enables seamless evaluation of NVMe IP core series and provides a convenient interface for testing and development with Altera FPGA platforms. This adapter board simplifies the integration of NVMe SSDs, optimizing performance for high-throughput applications in real-time systems.

Pepper - Agilex™ 5 based open source IoT and Network Gateway Platform

Pepper is Pantherun’s open-source FPGA development platform, built for real-time performance, secure networking, and rapid innovation — already inspiring hundreds of projects across universities and corporates

PIB

PIB is an intelligent development platform based on an Intel x86 i7 CPU and Cyclone V GT FPGA, designed for applications such as industrial control, vision optimization, and edge computing.

PPS Master (Pulse Per Second)

Full standalone hardware only Pulse Per Second generator

PPS Slave (Pulse Per Second)

Full standalone hardware only solution of a Pulse Per Second Slave (Sink)