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Altera Solutions
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Agilex™ 3 FPGA C-Series
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eASIC™ N3X Devices
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Agilex® 3 FPGAs and SoC FPGAs C-Series
Agilex® 5 FPGAs and SoC FPGAs D-Series
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Mustang Mesa
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Company Name

By Source

Altera Solutions
Partner Solutions

Offering Types

Acceleration / AI / Cloud
- Artificial Intelligence (AI)
- Data Processing / Analysis / Acquisition
- Data Science
- Edge
- Machine Learning
- Neural Network
- Public / On Premise
- Regional / District / Central
- Storage / Compression
Boards / SOMs / Dev Kits
- COTS
- Daughter Card
- Development / Evaluation Kit
- DPU / IPU / AI NIC / SmartNIC
- PCI Express
- System-on-Module (SOM)
- VPX
Design Services
- Board Level Design (DS)
- Certification (DS)
- Custom IP (DS)
- Debug (DS)
- Design for Manufacturing (DS)
- FPGA Design (DS)
- Logistics (DS)
- Manufacturing (DS)
- Schematic / Layout Review & DFT (DS)
- SI / PI Simulation (DS)
- Software (DS)
- System Level Design (DS)
- Verification / Validation (DS)
EDA Tools / IDE
- Design
- Embedded Tools
- Protocol Analysis
- Simulation
- Verification
Education / Training
- Acceleration / Artificial Intelligence (AI)
- Design Optimization
- Digital Signal Processing
- Embedded Processing
- External Memory Interfaces
- HDL Design Methodologies
- Interface Protocols
- Quartus Design Flow
- Security
Intellectual Property (IP)
- Digital Signal Processing / AI
  - Artificial Intelligence
  - Error Correction
  - Filters /Transforms
  - Floating Point
  - Modulation
  - Video and Image Processing
- Interfaces
  - Audio / Video
  - Communication
  - Compute Express Link (CXL)
  - Ethernet
  - High Speed
  - Networking / Security
  - PCI Express (IP)
  - Serial
- Memory Controllers
  - DMA
  - Flash
  - SDRAM
  - SRAM
- Soft Embedded Processors
  - RISC V
- Transceivers & Basic Functions
  - Clocks, PLLs and Resets
  - Simulation, Debug and Verification
  - Transceivers
Manufacturer
- Board Level Design (MF)
- Certification (MF)
- Custom IP (MF)
- Debug (MF)
- Design for Manufacturing (MF)
- FPGA Design (MF)
- Logistics (MF)
- Manufacturing (MF)
- Schematic / Layout Review & DFT (MF)
- SI / PI Simulation (MF)
- Software (MF)
- System Level Design (MF)
- Verification / Validation (MF)
Software / OS / RTOS
- Drivers
- Embedded
- Operating System (OS)
- Real Time Operating System (RTOS)
System Integrator / Provider
- Board Integration
- Chassis construction
- Chip Integration
- Software Integration

Region

Americas
Asia Pacific
Europe & Middle East
Japan
People’s Republic of China

Device Family

Agilex™ 3 FPGA C-Series
Agilex™ 5 FPGA D-Series
Agilex™ 5 FPGA E-Series
Agilex™ 7 FPGA F-Series
Agilex™ 7 FPGA I-Series
Agilex™ 7 FPGA M-Series
Agilex™ 9 FPGA Direct RF-Series
Arria® 10 Bare Die
Arria® 10 GT FPGA
Arria® 10 GX FPGA
Arria® 10 SX FPGA
Arria® II GX FPGA
Arria® II GZ FPGA
Arria® V GT FPGA
Arria® V GX FPGA
Arria® V GZ FPGA
Arria® V ST FPGA
Arria® V ST SoC FPGA
Arria® V SX FPGA
Arria® V SX SoC FPGA
Cyclone® 10 GX FPGA
Cyclone® 10 LP FPGA
Cyclone® II FPGA
Cyclone® III Bare Die
Cyclone® III FPGA
Cyclone® III LS FPGA
Cyclone® IV E FPGA
Cyclone® IV GX FPGA
Cyclone® V E FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Cyclone® V SE FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX FPGA
Cyclone® V SX SoC FPGA
eASIC™ N3X Devices
eASIC™ N3XS Devices
eASIC™ N5X Devices
Agilex® 3 FPGAs and SoC FPGAs C-Series
Agilex® 5 FPGAs and SoC FPGAs D-Series
Agilex® 5 FPGAs and SoC FPGAs E-Series
Agilex® 7 FPGAs and SoC FPGAs F-Series
Agilex® 7 FPGAs and SoC FPGAs I-Series
Agilex® 7 FPGAs and SoC FPGAs M-Series
Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series
Arria® 10 GT FPGA
Arria® 10 GX FPGA
Arria® 10 SX SoC FPGA
Cyclone® 10 GX FPGA
Cyclone® 10 LP FPGA
eASIC® N3X Devices
eASIC® N3XS Devices
eASIC™ N3X Devices
eASIC™ N3XS Devices
MAX® 10 FPGA
Stratix® 10 AX SoC FPGA
Stratix® 10 DX FPGA
Stratix® 10 GX FPGA
Stratix® 10 SX SoC FPGA
Stratix® 10 TX FPGA
MAX® 10 FPGA
MAX® II CPLD
MAX® II Z CPLD
MAX® V CPLD
Mustang Mesa
Stratix® 10 AX FPGA
Stratix® 10 Bare Die
Stratix® 10 DX FPGA
Stratix® 10 GX FPGA
Stratix® 10 SX FPGA
Stratix® 10 TX FPGA
Stratix® III FPGA
Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GX FPGA

Market Segments

Access
- Cable Access
- Carrier Access
- Other Access
Aerospace
- Aerospace
ASIC Proto
- ASIC Emulation
- ASIC Prototyping
Broadcast
- Broadcast Studio
- ProAV
Consumer
- Gaming
- Home Audio/Video
- Multi-Functional Printer
- Other Consumer
Defense
- MIL COMMS
- Radar/Ew
Industrial
- Energy
- Industrial / Manufacturing
- Robotics
- Vision
Government
- Chassis construction
- Drivers
- Govt Infrastructure
- Other ADG
- Software Integration
Medical
- Imaging
- Lab/Life Sciences
- Non-Imaging Patient Devices
- Other Medical
- Ultrasound
- Video
Data Center OEM (IHV, ISV, SI, VAR)
- AI/HPC
- CDNs
- IaaS/PaaS
- Networking
- Storage
- Transmission
Transportation
- Automotive (Passenger Vehicles)
- Non-Automotive Transportation
- Charging Infrastructure
- Transportation Infrastructure (non-charging)
Data Center Cloud (Public, Private, Hybrid)
- AI/HPC
- IaaS/PaaS
- Networking
- CDNs
- Storage
- Transmission
Wireless
- Baseband
- AI-RAN
- NTN/Fixed Wireless
- DAS/repeater/RIS
- xhaul Hub
- RDU
- FWA/backhaul
- 5G/ 6G Radio
Test
- ATE
- RF Instrumentation
- Communication Tester
- Other Test

Program Level

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Select

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Sort by

Sort By: A -> Z

Sort By: Z -> A

Sort By: Oldest first

Sort By: Newest first

Serial FPDP (sFPDP) 17.1

iWave’s sFPDP IP Core delivers low-latency, high-throughput serial communication for real-time applications like radar and electronic warfare. Supporting up to 4.25 Gbps and multiple operating modes, it ensures reliable, high-speed data transport in mission-critical environments. In simple terms, it is used to communicate from 1 system to another system over serial interface.

By iWave Global

View Details

Serial Lite IP

The Serial Lite FPGA IP core is a simple, low-latency, scalable protocol for high-bandwidth serial data transfer applications. It is suitable for high-bandwidth data communication for chip-to-chip, board-to-board, and backplane applications. The core incorporates a media access control (MAC), physical coding sublayer (PCS), and physical media attachment (PMA) block.

By Altera

View Details

Serial RapidIO controller (Silicon Proven IP for Altera Devices)

The GRIO (Generic RapidIO) Controller is a fully synchronous IP with low-latency, high-bandwidth RapidIO interface support. It can act as a host or device and is designed for ease of migration across silicon technologies. Its flexible backend interface allows integration into wide-ranging embedded and communication applications.

By Mobiveil Inc.

View Details

SHA 256 IP

Design Gateway’s SHA-256 IP core provides an efficient and secure solution for implementing the SHA-256 hashing function. Optimized for hardware, this IP core offers high throughput with 7.875 Mbps per MHz, processing 512-bit data blocks in just 65 clock cycles. Its hardware-based design ensures low latency, making it suitable for applications such as secure password hashing, digital signatures, and blockchain technology. The SHA-256 IP core is easy to integrate, with a reference design and demo files available for quick evaluation on FPGA platforms.

By DesignGateway Co., Ltd.

View Details

SHA-256: 256-bit SHA Secure Hash Crypto Engine

The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (2^64 – 1) bits. Developed for easy reuse in ASIC and FPGA applications, the SHA-256 is available optimized for several technologies with competitive utilization and performance characteristics. Support for AMBA bus interfaces and integration with an external DMA are available as options "

By Computer Aided Software Technologies, Inc (dba CAST)

View Details

SHA-3: Secure Hash Crypto Engine

The SHA-3 IP core is a high-throughput, area-efficient hardware accelerator for SHA-3 cryptographic hashing, compliant with NIST FIPS 180-4 and FIPS 202. It operates independently of a host processor, using AMBA® AXI4-Stream interfaces for input and output. An optional AXI4-Stream to AXI4 Memory Mapped bridge, with or without DMA, can be used. A single core instance implements all fixed-length and extendable-output hash functions, with function and output length (up to 2 GB) selectable at runtime per input message. The core is highly configurable at synthesis, including bus width and SHA-3 permutation rounds per cycle, enabling throughput–area trade-offs. One permutation per cycle processes 50 bits per cycle, scaling to over 100 Gbps with multiple permutations in modern ASICs. Fully synchronous, single-clock, scan-ready, LINT-clean, it uses only rising-edge flip-flops, with no false or multi-cycle paths, simplifying integration and verification.

By Computer Aided Software Technologies, Inc (dba CAST)

View Details

Side Channel Attack & Fault Injection

Side-Channel Power Analysis - that freaky method of extracting secret keys from embedded systems that doesn’t rely on exploits or coding errors. It can be used to read out an AES-128 key in less than 60 seconds from a standard implementation on a small microcontroller. Are your products vulnerable to such an attack? This course is loaded with hands-on examples to teach you not only about the attacks and theories, but how to apply them. Fault Injection Attacks - can you even trust your hardware? This training will cover fault injection attacks (also known as glitch attacks) on embedded systems. These attacks allow you to entirely bypass security mechanisms, dump memory over communication interfaces, and wreak havoc for fun and profit. Countermeasures - Easy to grasp examples example vulnerable implementations are discussed along with industry best practices to counter and mitigate the advanced hardware attacks.

By HandsOn-Training

View Details

Signal Generator

Time aligned Signal Generator

By NetTimeLogic GmbH

View Details

Signal Timestamper

Time aligned Signal Timestamper

By NetTimeLogic GmbH

View Details

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Serial FPDP (sFPDP) 17.1

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Serial RapidIO controller (Silicon Proven IP for Altera Devices)

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SHA-256: 256-bit SHA Secure Hash Crypto Engine

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Side Channel Attack & Fault Injection

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Serial FPDP (sFPDP) 17.1

Serial Lite IP

Serial RapidIO controller (Silicon Proven IP for Altera Devices)

SHA 256 IP

SHA-256: 256-bit SHA Secure Hash Crypto Engine

SHA-3: Secure Hash Crypto Engine

Side Channel Attack & Fault Injection

Signal Generator

Signal Timestamper