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TR10a-HL Arria® 10 FPGA Development Kit

Terasic TR10a-HL Development Kit provides the ideal hardware solution for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency communication, and power efficiency. With a full-height, 1/2-length form-factor package, the TR10a-HL is designed for the most demanding high-end applications, empowered with the top-of-the-line Altera Arria 10 GX, delivering the best system-level integration and flexibility in the industry.

TR10a-HL2 Arria® 10 FPGA Development Kit

Terasic’s TR10a-HL2 is designed to advance the agility, flexibility and speed and delivers blazing performance in cloud and data center applications.

Transparent Compression

Eideticom’s NoLoad Transparent Compression delivers high-performance inline data compression. Its NVMe-compliant interface ensures native driver support across all CPU platforms and operating systems, including Linux, FreeBSD, and Windows.

Triple-Speed Ethernet FPGA IP

A complete 10/100/1000 Mbps Ethernet IP with flexible IP options including MAC only, PCS only, MAC + PCS, MAC + PCS + PMA, PCS + PMA.

TSN End-Node (IEEE802.1 Time Sensitive Networking End-Node)

Full standalone hardware only solution of a TSN End-Node

TSN Network Node (IEEE802.1 Time Sensitive Networking Switched End-Node)

Full hardware only solution for a TSN Switched End-Node

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TSN-EP: TSN Ethernet Endpoint Controller

The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS-2020) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC. Enhanced reliability features can also be sup ported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci).

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TSN-SE: TSN Ethernet Switched Endpoint Controller

"The TSN-SE is a highly configurable two-port Switched Endpoint Controller IP core tailored for Time-Sensitive Networking (TSN) Ethernet systems. It embeds hardware support for 802.1AS-2020 timing synchronization, 802.1Qav/Qbv traffic shaping, 802.1Qbu/802.3br frame preemption, plus two low-latency Ethernet MACs. Optional modules enable enhanced reliability with 802.1CB frame replication and elimination, and 802.1Qci per-stream filtering and policing. Designed for daisy-chained or ring topologies and bridged endpoints, TSN-SE delivers precise, deterministic ingress/egress latency via cut-through switching and minimal buffering, simplifying time-aware application development. It provides real-time timing data timestamps, alarms, and allows dynamic traffic-shaping configuration. Integration is seamless via standard AMBA® interfaces: a 32-bit APB bus for control/status, and 32-bit AXI-Streaming for packet I/O. Optional DMA engine and software stacks are also available.

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TSN-SW: TSN Ethernet Switch

The TSN-SW implements a highly flexible, low-latency, multiport TSN Ethernet switch. It supports the hardware functionality for Ethernet bridging according to the IEEE 802.1Q standard and implements the essential TSN timing synchronization and traffic-shaping protocols (i.e. IEEE 802.1AS-2020, 802.1Qav, 802.1Qbv, and 802.1Qbu, 802.1br). Enhanced reliability features can also be supported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci). Featuring a configurable number of ports, the Layer-2 switch operates in cut-through mode at wire speed and can provide sub-microsecond port-to-port latency. The core is hence suitable for applications with demanding real-time requirements.