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TSoM

TSoM is a pocket-sized module powered by the latest Intel Cyclone® V SoC FPGA. The board itself takes advantage of the ARM dual-core Cortex-A9 CPU and 110K FPGA Logic Elements to achieve lowest system cost and power efficiency. Armed with 1GB DDR3 memory for FPGA and HPS fabric respectively, and up to 8GB eMMC flash, the Cyclone V module ideally suited for building high bandwidth and large capacity memory system for a wide range of embedded applications.

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Turbo-V FPGA IP Core

Turbo codes assist in forward error correction systems. You can use Turbo codes in other applications that require reliable information transfer over bandwidth- or latency-constrained communication links in the presence of data-corrupting noise.

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U.2-PCIe adapter board for PCIe Gen5 SSD (AB20-U2PCI)

AB20-U2PCI board converts 16-lane PCI Express interface to four 4-lane PCI standard U.2 interfaces, supporting PCIe Gen5 speeds. This adapter can be applied to Altera FPGA evaluation boards so that user can evaluate NVMe series IP Core operation and can use for prototype development platform.

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UDPIP-100G: 100G UDP/IP Hardware Protocol Stack

Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 100 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.

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UDPIP-10G/25G: 10G/25G UDP/IP Hardware Protocol Stack

Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 25 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.

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UDPIP-1G: UDP/IP Hardware Protocol Stack

Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 10 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.

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UDPIP-40G/50G: 40G/50G UDP/IP Hardware Protocol Stack

Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 50 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.

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UHS OPI PSRAM Controller (Silicon Proven IP for Altera Devices)

Targeted at wearables and low-power devices, Mobiveil’s UHS OPI PSRAM Controller supports AP Memory’s UHS series running up to 1066 MHz. It delivers low-power, high-frequency performance for memory subsystems with simplified interface requirements. The flexible architecture ensures precise control signal timing for seamless SoC integration.

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Ultra-high-throughput WiFi LDPC Decoder

XCEL ASICs’ Ultra-High-Throughput Wi-Fi LDPC Decoder IP is an IEEE 802.11n/ac/ax/be–compliant (Wi-Fi 4/5/6/7) forward error correction (FEC) solution optimized for current and next-generation Wi-Fi transceivers and SoC designs. In addition to supporting earlier Wi-Fi generations, the IP enables Wi-Fi 7 (IEEE 802.11be) data rates exceeding 30 Gbps while delivering exceptional throughput-per-area efficiency, enabling very high decoding performance within a minimal silicon footprint. This combination of scalable throughput and area efficiency makes the IP particularly well suited for cost- and power-constrained, high-performance Wi-Fi transceiver chip implementations.

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Showing 595-603 of 667 Offerings