This device configuration support page provides resources for Altera® FPGA devices. 

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FPGA offers a wide range of configuration solutions to configure FPGA devices. Note that different FPGA devices support different configuration schemes.

For general comparisons, go to the section on "Configuration Schemes Comparison."

In general, Altera® FPGA configuration schemes are categorized into active configuration schemes or passive configuration schemes. In the active configuration schemes, the device controls the configuration process and gets the configuration data from an external memory device. Active serial (AS) and active parallel (AP) are active configuration schemes. The memory device is a serial configuration (EPCQ) device for AS configuration and a supported parallel flash memory for AP configuration.

In the passive configuration schemes, the configuration device controls the configuration process and supplies the configuration data. The configuration device can be an external intelligent host, such as a PC, a microprocessor, or a MAX® series CPLD. Passive serial (PS), fast passive parallel (FPP), and JTAG are passive configuration schemes.

External Memory and/or Configuration Device

All configuration schemes require either an external memory or a configuration device. These external devices are necessary to store configuration data and/or configure the Altera® FPGA when using a particular configuration scheme. For example, an external memory device can be a serial configuration (EPCQ) device or a supported parallel flash memory device. A configuration controller can be a microprocessor or any MAX® series CPLD. Note that different configuration schemes are supported by different external memories and/or configuration devices. The MAX® series CPLD supports Parallel Flash Loader intellectual property (IP) to program common flash interface (CFI) flash memory devices through the JTAG interface and provides the logic to control configuration (Passive Serial and Fast Passive Parallel) from the flash memory device to the FPGA.

• Parallel Flash Loader FPGA IP User Guide
   
• MAX® Series Configuration Controller Using Flash Memory White Paper

Width of DATA Bus

The width of the DATA bus determines the number of bits transmitted per DCLK cycle for the configuration scheme. In general, the configuration schemes can also be grouped in either serial configuration schemes or parallel configuration schemes. Serial configuration schemes transmit 1 bit per DCLK cycle. PS, AS, and JTAG are serial configuration schemes. On the other hand, parallel configuration schemes transmit more than 1 bit per DCLK cycle. The FPP configuration schemes transmit 8, 16, and 32 bits per DCLK cycle. The AP configuration scheme transmits 16 bits per DCLK cycle. Generally, the higher number of DATA bits transmitted per DCLK cycle contributes to a shorter configuration time.

Relative Configuration Time

The configuration cycle consists of three stages: reset, configuration, and initialization. The relative configuration times here refer only to the configuration stage. The time it takes for the device to enter user mode is actually longer.

Configuration time varies for different configuration schemes and depends on the configuration file size, configuration data width, frequency of the driving clock, and flash access time. You can estimate the relative configuration time between various configuration schemes of the same device family and density.

AS configuration time is dominated by the time it takes to transfer data from the EPCQ to the FPGA device. The AS interface is clocked by the FPGA DCLK output generated from an internal oscillator. The DCLK minimum frequency when using the 40 MHz oscillator is 20 MHz (50 ns). For example, the maximum AS configuration time estimate for an EP3C10 device is (2.5 Mb of uncompressed data) = RBF size x (maximum DCLK period / 1 bit per DCLK cycle) = 2.5 Mb x (50 ns / 1 bit) = 125 ms.

In general, the FPP configuration schemes have the shortest configuration times. For all the FPP schemes, the configuration frequency is controlled by the external device. The AS, PS, and JTAG configuration schemes have a relatively slower configuration time. However, the relative configuration time is just an estimate. The actual configuration time depends heavily on the configuration data width, the configuration frequency at which the device is clocked, the configuration file size, and the flash access time.

Support for CLKUSR Feature

In some devices, the CLKUSR pin is an optional pin that inputs a user-supplied clock to synchronize the initialization of one or more devices after configuration. This feature allows one or more devices to enter user mode at the same time. This pin is enabled by turning on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus® Prime or Quartus II software.

Scalability

The Altera® FPGA EPCS devices and EPCQ devices support a single-device configuration solution for Agilex® series, Stratix® series (except for Stratix® and Stratix® GX), Arria® series, and Cyclone® series FPGAs.

To choose the appropriate configuration device, you must determine the total configuration space required for your target FPGA or chain of FPGAs. If you are configuring a chain of FPGAs, you must add the configuration file size for each FPGA to determine the total configuration space needed.

Configuration via Protocol (CvP)

Configuration via Protocol (CvP) is a configuration scheme that allows you to configure the FPGA fabric via the PCI Express (PCIe*) interface for various devices.

The autonomous PCIe hard intellectual property (IP) allows the embedded PCIe core to operate before the FPGA is fully configured. This enables the FPGAs to easily meet the PCIe wake-up time requirement.

Configuration via Protocol Support provides resources for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, Cyclone® 10, Stratix® V and Arria® V devices.

Reference solutions to configure and program Altera® FPGA devices.

• FPGA Configuration Troubleshooter