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10G UDP Offloading Engine (UDP10G-IP)

DesignGateway Co., Ltd.

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Design Gateway’s UDP-IP core series offers a fully hardware-based UDP/IP stack, eliminating the need for external CPUs. This pure hardware logic design ensures high throughput, making it ideal for systems where real-time responsiveness and consistent performance are critical. Key features of the UDP-IP core series include customizable buffer sizes, user-friendly interfaces (FIFO for data and register-based for control), and support for multicast and broadcast transmissions. When combined with Design Gateway's optimized EMAC-IP, the solution achieves high-throughput with minimizing resource and latency. Comprehensive reference designs and evaluation files are available for Altera FPGA platforms, facilitating rapid development and deployment. With a proven track record in mission-critical fields such as aerospace and defense, Design Gateway's UDP-IP cores deliver reliable and scalable performance for high-speed network communication. By offloading the ...

Design Gateway’s UDP-IP core series offers a fully hardware-based UDP/IP stack, eliminating the need for external CPUs. This pure hardware logic design ensures high throughput, making it ideal for systems where real-time responsiveness and consistent performance are critical. Key features of the UDP-IP core series include customizable buffer sizes, user-friendly interfaces (FIFO for data and register-based for control), and support for multicast and broadcast transmissions. When combined with Design Gateway's optimized EMAC-IP, the solution achieves high-throughput with minimizing resource and latency. Comprehensive reference designs and evaluation files are available for Altera FPGA platforms, facilitating rapid development and deployment. With a proven track record in mission-critical fields such as aerospace and defense, Design Gateway's UDP-IP cores deliver reliable and scalable performance for high-speed network communication. By offloading the entire UDP/IP stack to hardware, they minimize CPU workload and ensure stable operation even under demanding conditions.

Key Features

  • Pure hardware-based UDP/IP stack with IPv4 and IP fragmentation support
  • Configurable buffer sizes and 64-bit FIFO interface for high-throughput data transfer
  • Full-duplex communication and multi-session support using multiple UDP10G IPs
  • Multicast/broadcast Tx feature customization
  • Reference designs available for Altera FPGA evaluation kits
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Offering Brief

Offering Brief

Device Family Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® 10 SX SoC FPGA, Arria® 10 GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available Yes
Demo Yes
Compliance No
Latest Quartus Version Supported 24.1.0
Development Language Encrypted VHDL

Encrypted IP core

Reference Designs Quartus Project

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