Cyclone® V GX FPGA

Cyclone® V GX FPGA is optimized for lowest cost and power for 614 Mbps to 3.125 Gbps transceiver applications.

Benefits

Do More with Less Power, Design Time, and Cost

It is built on TSMC's 28 nm low-power (28LP) process technology, including hard intellectual property (IP) blocks, allowing you to differentiate and do more.

Logic Integration and Differentiation Capabilities

It offers an 8-input adaptive logic module (ALM) and variable-precision digital signal processing (DSP) blocks, allowing up to 13.59 megabits (Mb) of embedded memory.

Increased Bandwidth Capacity

With hard memory controllers, leverage increased transceiver bandwidth capacity ranging from 614 Mbps to 3.125 Gbps.

Key Features

Internal memory blocks

M10K: 10-kilobits (Kb) memory blocks with soft error correction code (ECC). Memory logic array block (MLAB): 640-bit distributed LUTRAM where you can use up to 25% of the ALMs as MLAB memory.

General-purpose I/Os

875 megabits per second (Mbps) low-voltage differential signaling (LVDS) receiver and 840 Mbps LVDS transmitter. 400 MHz/800 Mbps external memory interface. On-chip termination (OCT). 3.3 V support with up to 16 mA drive strength.

PCIe Hard IP

Cyclone® V GX devices contain PCIe* hard IP that is designed for performance and ease-of-use. The PCIe* hard IP consists of the MAC, data link, and transaction layers.

Low-power serial transceivers

Cyclone® V devices deliver the industry’s lowest power 6.144 Gbps transceivers at an estimated 88 mW maximum power consumption per channel.