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MIPI D-PHY IP

Altera

Mobile Industry Processor Interface (MIPI) D-PHY is supported on Agilex™ 5 and Agilex™ 3 FPGAs allowing transmission and reception of data through PHY-protocol interface (PPI) to connect with camera serial interface (CSI) and display serial interface (DSI) applications.

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Key Features

  • MIPI D-PHY
  • MIPI D-PHY feature supports high-speed (HS) and low-power (LP) modes and allows direct interface with the D-PHY compliance component without external components
  • Supports low-power and high-speed signaling up to 3.5 Gbps per lane, supports AXI-Lite interface for seamless video transmission and reception, enables unidirectional multi-lane configurations 1, 2, 4, or 8 lanes
  • MIPI CSI-2
  • Latency Reduction and Transport Efficiency (LRTE) for image-sensor aggregation without adding to the overall system cost, Differential Pulse Code Modulation (DPCM) compression for seamless compression of HD images for mission critical applications,
  • Reducing the number of wires in a system like IoT by using the Unified Serial Link (USL), Scrambling reduces Power Spectral Density (PSD) emissions for longer channels
  • MIPI DSI-2:
  • High Resolution Support: MIPI DSI-2 supports high-resolution displays, including 4K, 5K UHD+, and 8K UHD resolutions, VESA Display Compression-M (VDC-M) Compliance: It is compliant with VESA VDC-M 1.2
  • Supporting various encoding mechanisms like BP, transform, MPP, MPP fallback, and BP skip, Flexible Video Input Formats: Supports 8, 10, or 12 bits per component video, with 4:4:4 sampling for RGB and 4:4:4, 4:2:2, and 4:2:0 sampling for YCbCr video input
  • High Pixel Throughput: Capable of processing two pixels per clock per hard slice encoder, with parameterizable parallel slice encoder instances to adapt to different display resolutions
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Offering Brief

Offering Brief

Device Family Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 3 FPGAs and SoC FPGAs C-Series
Offering Status Production
Demo No
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Compliance No
Development Language Encrypted Verilog

Encrypted Verilog source code

Design Examples

Simulation Models

IP Evaluation Mode

Documentation: IP User Guide, Example Design User Guide, IP Release Notes

Ordering Information

IP-MIPI-CSI-2

from Direct

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