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XAUI PHY FPGA IP

Altera

The XAUI PHY FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Altera FPGA to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module.

Key Features

  • Complete 10G Ethernet (XAUI) PHY solution for 4X 3.125 Gbps serial external interface
  • PHY consisting of 10GBASE-X physical coding sublayer (PCS)
  • Physical medium attachment (PMA)
  • XGMII Extender Sublayer (XGXS), 10G Ethernet (XAUI), and PHY management functions
  • Direct interface with 10GbE MAC for a complete solution, Direct standard XAUI PHY (4X 3.125 Gbps) connection for chip-to-chip, chip-to-optical module, chip-to-PHY device, backplane, and short cable applications
  • PHY and soft XAUI PCS supported on many FPGA device families including: Stratix® IV, Stratix® V, Arria® V, and Arria® 10 FPGAs with serial transceivers
  • Data and control bits 8b/10b encoding/decoding and per-lane synchronization, data serialization/deserialization (SERDES) to and from 4X 3.125 Gbps line
  • Receiver four-data lane alignment, deskew, and alignment of four lanes, and receiver rate matching for clock frequency compensation
  • Dynamic partial reconfigurable I/O (DPRIO) support
  • Local serial loopback from transmitter to receiver at the device's serial transceiver for self-testing
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Offering Brief

Offering Brief

Device Family
Offering Status Production
Integrated Testbench Yes
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Development Language Encrypted Verilog

Encrypted Verilog source code

Simulation Models

Documentation: User Guide, Release Information

Ordering Information

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