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Reed Solomon II FPGA IP Core

Altera

The Reed Solomon II FPGA intellectual property (IP) core offers a fully parameterizable Reed Solomon encoder and decoder. These encoders and decoders are widely used for error detection and correction in a wide range of digital signal processing (DSP) applications for storage, retrieval, and transmission of data. The Reed Solomon II Intel FPGA IP core is designed to support optical transport network (OTN) applications.

Key Features

  • Number of symbols per code word (range: 204 to 255)
  • High-performance greater than 100 Gbps encoder or decoder for error detection and correction
  • Multichannels and backpressure for decoders
  • Fracturable decoder that supports 100 Gbps Ethernet (GbE), 2 x 50 GbE, and 4 x 25 GbE, Avalon® Streaming (Avalon-ST) interfaces
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Offering Brief

Offering Brief

Device Family Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, MAX® 10 FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Development Language Encrypted Verilog, Encrypted VHDL

Encrypted Verilog source code

Design Example

Simulation Models

IP Evaluation Mode

Documentation: IP User Guide, IP Release Notes

Ordering Information

Market Segment and Sub-Segments