This is a complete 10/100/1000 Mbps Ethernet IP with flexible options including MAC only, PCS only, MAC + PCS, MAC + PCS + PMA, and PCS + PMA. In MAC-only mode, the IP uses an external PHY chip to do signaling. The two supported interfaces to the external PHYs are GMII (8-bit interface at 125 MHz SDR) and RGMII (4-bit interface at 125 MHz DDR). In the MAC+PHY mode, the PHY is realized using on-chip transceivers or LVDS I/O with dynamic phase alignment (DPA) logic that can operate up to 1.25 Gbps. SGMII or 1000Base-X protocol is used in this case. The usage of LVDS I/Os enables very scalable multiport gigabit Ethernet (GbE) system designs while saving the serial transceivers for higher performance protocols.