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Triple-Speed Ethernet FPGA IP

Altera

This is a complete 10/100/1000 Mbps Ethernet IP with flexible options including MAC only, PCS only, MAC + PCS, MAC + PCS + PMA, and PCS + PMA. In MAC-only mode, the IP uses an external PHY chip to do signaling. The two supported interfaces to the external PHYs are GMII (8-bit interface at 125 MHz SDR) and RGMII (4-bit interface at 125 MHz DDR). In the MAC+PHY mode, the PHY is realized using on-chip transceivers or LVDS I/O with dynamic phase alignment (DPA) logic that can operate up to 1.25 Gbps. SGMII or 1000Base-X protocol is used in this case. The usage of LVDS I/Os enables very scalable multiport gigabit Ethernet (GbE) system designs while saving the serial transceivers for higher performance protocols.

Key Features

  • Flexible IP options: MAC only, PCS only, MAC + PCS, MAC + PCS + PMA, PCS + PMA
  • Sizes as small as 900 logic elements (small-MAC)
  • Standard-based statistics counters supporting simple network management protocol (SNMP), management information base (MIB and MIB-II) and remote network monitoring (RMON)
  • IEEE 1588v2 high accuracy and high precision time stamping option in hardware IP
  • Real time of day clock generator (ToD) IP in design example
  • Many external Ethernet interface options for various FPGA families such as MII (10/100 Mbps), GMII, RGMII, and SGMII (10/100/1000 Mbps), 1000BASE-X, and TBI (1 Gbps)
  • Management data I/O (MDIO) for external PHY device management
  • Parameterizable FIFO or FIFO-less MAC options
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Offering Brief

Offering Brief

Device Family Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, MAX® 10 FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo Yes
Compliance No
Development Language Encrypted Verilog

Encrypted Verilog Source Code

Design Example

Simulation Models

IP Evaluation Mode

Documentation: IP User Guide, Design Example User Guide, IP Release Notes

Ordering Information

Documentation & Resources

Market Segment and Sub-Segments