1G/10Gb Ethernet PHY FPGA IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

The 1G/10G Ethernet PHY FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher data rate 10G PCS with an appropriate physical medium attachment (PMA). The Standard PCS implements the 1GbE protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard and also supports auto-negotiation as defined in Clause 37 of the IEEE 802.3 2005 Standard. The 10G PCS implements the 10G Ethernet protocol as defined in the IEEE 802.3 2005 standard. The user can switch dynamically between the 1G and 10G PCS using the Transceiver Reconfiguration Controller IP core to reprogram the core. This IP core targets 1G/10GbE applications including network interfaces to 1G/10GbE dual speed SFP+ pluggable modules, 1G/10GbE 10GBASE-T copper external PHY devices to drive CAT 6/7 shielded twisted-pair cables, and chip-to-chip interfaces.

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Key Features

Integrated SGMII / 1000BASE-X / 10GBASE-R (10M-10Gb) Ethernet PCS and PMA
Direct internal interface with 1G/10GbE (10M-10GbE) MAC for a complete single-chip solution
User selectable 1G/10Gb data rates during runtime or automatic speed detection (parallel-detect) between 1Gb and 10Gb and reconfiguration by PHY IP, or data rate selection among 10/100/1000Mb with Ethernet Auto-Negotiation function
IEEE 1588v2 option
Synchronous Ethernet (Sync-E) option: 1) Serial transceiver clock and data recovery (CDR) recovered clock output signal exposed to the FPGA fabric for routing to a Sync-E jitter cleaner phase-locked loop (PLL)
Separate transmitter (TX) and receiver (RX) serial transceiver PLL reference clock inputs to allow optional external Sync-E jitter cleaner PLL to feed the cleaned clock to TX PLL reference clock input
Local serial loop-back from transmitter to receiver at serial transceiver for self-test
High-performance internal system interfaces
Avalon Memory-Mapped (Avalon-MM) 32 bit interface for management
10Gb, 1G/10GE, and 10M-10GE (SGMII/1G/10GE) options
Receiver-link fault status detection
GMII and single data rate (SDR) XGMII interfaces to 1G/10GbE (10M-10GbE) MAC, 8 bits at 125 MHz, and 72 bits at 156.25 MHz respectively for data transfer

Offering Brief

Device Family	Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Development Language	Encrypted Verilog