Agilex 7 and Stratix 10 FPGA E-Tile Hard IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

The Agilex 7 and Stratix 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible with the IEEE 802.3 High-Speed Ethernet Standard and the 25G and 50G Ethernet Specification, Draft 1.6 from the 25G Ethernet Consortium. The Intellectual Property (IP) core provides access to this hard IP at data rates of 10 Gbps, 25 Gbps, and 100 Gbps. The MAC provides cut-through frame processing to optimize latency and supports full wire line speed with a 64-byte frame length and back-to-back or mixed-length traffic with no dropped packets. All IP core variations are in full-duplex mode. This IP core is available in multiple variants, each providing a different combination of Ethernet channels and features: 1) One to four 10GbE/25GbE channels with optional Reed-Solomon Forward Error Correction (RS-FEC). 2) 100G channel with optional RS-FEC for either CAUI-4 or CAUI-2 mode. 3) Dynamic configuration between one to four single 10GE/25GE channels or ...

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Key Features

The PHY supports: 1) CAUI external interface consisting of four FPGA hard serial transceiver lanes operating at 25.78125 Gbps. CAUI-2 external interface with two transceiver lanes operating at 53.125 Gbps with PAM4 encoding. 2) CAUI-4 links based on 64B/66B encoding with data striping and alignment markers to align data from multiple lanes. 3) Optional Reed-Solomon Forward Error Correction RS-FEC (528,514) or RS-FEC (544,514). 4) 10G, 25G, and 100G variations. 5) Auto-Negotiation (AN) and Link Training (LT)
This IP also supports 1) Jumbo packets. 2) RX CRC checking and error reporting. 3) IEEE Standard 1588v2 PTP. 4) Dynamic reconfiguration. 5) Avalon Memory-Mapped (Avalon-MM) management interface and Avalon-ST datapath interface

Offering Brief

Device Family	Agilex® 7 FPGAs and SoC FPGAs F-Series, Stratix® 10 GX FPGA, Stratix® 10 TX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Development Language	Encrypted Verilog