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40G Ethernet MAC and PHY FPGA IP

Altera

The 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010. 40 Gbps Ethernet is an industry standard and is compliant for media access control (MAC) and PHY (PCS + PMA) functions. It enables an FPGA to interface to another device over a copper or optical transceiver module. The IP supports IEEE 1588 v2 standard with two-step timestamping as well as backplane capability on a variety of Stratix or Arria FPGAs.

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Key Features

  • Compliant with the IEEE 802.3ba-2010 40 Gbps Ethernet standard
  • 40GE MAC soft IP with configurable feature set: 1) MAC+PHY, PHY-only, or MAC-only. 2) Transmitter plus receiver (full-duplex), transmitter-only, or receiver-only
  • Programmable maximum receive frame length up to 9,600 bytes
  • Promiscuous (transparent) and non-promiscuous (filtered) MAC operation modes
  • Programmable link fault signaling
  • Management data input/output (MDIO) or 2-wire serial interfaces for managing different optical modules; Passed functional and performance tests with 40/100Gb Ethernet test equipment
  • XLAUI physical medium attachment (PMA) hard IP and external interface consisting of serial transceiver lanes each operating at 10.3125 Gbps
  • 40GE physical coding sublayer (PCS) soft IP implemented in the FPGA fabric
  • PCS bit error rate (BER) monitor
  • Avalon streaming interface (Avalon-ST) for MAC datapath to client application
  • Avalon Memory Mapped (Avalon-MM) 32-bit interface for control and monitoring of MAC, PCS, PMA, and external optical module
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Offering Brief

Offering Brief

Device Family Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® V GS FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo Yes
Compliance No
Development Language Encrypted Verilog

Encrypted Verilog source code

Design Example

Simulation Models

IP Evaluation Mode

Documentation: IP User Guide, Design Example User Guide, IP Release Notes

Ordering Information

IP-40GEMAC; IP-40GEPHY; IP-40GEMACPHY; IP-40GBASEKR4PHY; IP-40GEUMACPHY; IP-40GEUMACPHYF; IP-40GBAS

from Digikey

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IP-40GEMAC; IP-40GEPHY; IP-40GEMACPHY; IP-40GBASEKR4PHY; IP-40GEUMACPHY; IP-40GEUMACPHYF; IP-40GBAS

from Mouser

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IP-40GEMAC; IP-40GEPHY; IP-40GEMACPHY; IP-40GBASEKR4PHY; IP-40GEUMACPHY; IP-40GEUMACPHYF; IP-40GBAS

from Mouser

Order Now

IP-40GEMAC; IP-40GEPHY; IP-40GEMACPHY; IP-40GBASEKR4PHY; IP-40GEUMACPHY; IP-40GEUMACPHYF; IP-40GBAS

from Digikey

Order Now

IP-40GEMAC; IP-40GEPHY; IP-40GEMACPHY; IP-40GBASEKR4PHY; IP-40GEUMACPHY; IP-40GEUMACPHYF; IP-40GBAS

from Digikey

Order Now

IP-40GEMAC; IP-40GEPHY; IP-40GEMACPHY; IP-40GBASEKR4PHY; IP-40GEUMACPHY; IP-40GEUMACPHYF; IP-40GBAS

from Mouser

Order Now

IP-40GEMAC; IP-40GEPHY; IP-40GEMACPHY; IP-40GBASEKR4PHY; IP-40GEUMACPHY; IP-40GEUMACPHYF; IP-40GBAS

from Digikey

Order Now

IP-40GEMAC; IP-40GEPHY; IP-40GEMACPHY; IP-40GBASEKR4PHY; IP-40GEUMACPHY; IP-40GEUMACPHYF; IP-40GBAS

from Mouser

Order Now

IP-40GEMAC; IP-40GEPHY; IP-40GEMACPHY; IP-40GBASEKR4PHY; IP-40GEUMACPHY; IP-40GEUMACPHYF; IP-40GBAS

from Mouser

Order Now

IP-40GEMAC; IP-40GEPHY; IP-40GEMACPHY; IP-40GBASEKR4PHY; IP-40GEUMACPHY; IP-40GEUMACPHYF; IP-40GBAS

from Digikey

Order Now

IP-40GEMAC; IP-40GEPHY; IP-40GEMACPHY; IP-40GBASEKR4PHY; IP-40GEUMACPHY; IP-40GEUMACPHYF; IP-40GBAS

from Mouser

Order Now

IP-40GEMAC; IP-40GEPHY; IP-40GEMACPHY; IP-40GBASEKR4PHY; IP-40GEUMACPHY; IP-40GEUMACPHYF; IP-40GBAS

from Mouser

Order Now

IP-40GEMAC; IP-40GEPHY; IP-40GEMACPHY; IP-40GBASEKR4PHY; IP-40GEUMACPHY; IP-40GEUMACPHYF; IP-40GBAS

from Digikey

Order Now

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