50G Ethernet FPGA IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

The 50G Ethernet FPGA IP core implements the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet draft. The IP core includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The MAC client side interface for the 50 Gbps Ethernet IP core is a 128-bit Avalon streaming interface (Avalon-ST). It maps to two 25.78125 Gbps transceivers. The IP core provides standard media access control (MAC), physical coding sublayer (PCS), and PMA functions. The PHY comprises the PCS and PMA.

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Key Features

Soft PCS logic that interfaces seamlessly to Agilex F-Tile FPGA 51.5625 gigabits per second (Gbps) serial transceiver
TX automatic frame padding to meet the 64-byte minimum Ethernet frame length
Optional RX strict SFD checking per IEEE specification
Unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard
Programmable serial PMA local loopback (TX to RX) at the serial transceiver for self-diagnostic testing; Avalon Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers
Avalon streaming (Avalon-ST) data path interface connects to client logic
Ready latency of 0 clock cycles for Avalon-ST TX interface
Support for jumbo packets
RX CRC checking and error reporting
RX malformed packet checking per IEEE specification

Offering Brief

Device Family	Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Arria® 10 GT FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Development Language	Encrypted Verilog