Stratix 10 FPGA H-Tile Hard IP for Ethernet

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

Stratix 10 FPGA H-Tile production devices include a configurable, hardened protocol stack for Ethernet that is compatible with the IEEE 802.3 High Speed Ethernet Standard. The Stratix 10 H-Tile Ethernet Hard IP core is available with a 100GBASE-R4 Ethernet channel. For the Ethernet data rate, you can choose a media access control (MAC) + physical coding sublayer (PCS) variation or a PCS-only variation. The 100GBASE-R4 Ethernet channel maps to four 25.78125 Gbps links. The FPGA serial transceivers are compliant with the IEEE 802.3-2015 High Speed Ethernet Standard CAUI-4 specification. The IP core configures the transceivers to implement the relevant specification for your IP core variation. You can connect the transceiver interfaces directly to an external physical medium dependent (PMD) optical module or to another device.

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Key Features

The MAC provides cut-through frame processing to optimize latency and supports full wire line speed with a 64-byte frame length and back-to-back or mixed length traffic with no dropped packets
Full-duplex mode for all variations
Hard IP logic that interfaces seamlessly to Stratix 10 FPGA 25.78125 Gbps serial transceivers
LAUI or CAUI-4 external interface consisting of two or four FPGA hard serial transceiver lanes operating at 25.78125 Gbps
Supports LAUI or CAUI-4 links based on 64B/66B encoding with data striping and alignment markers to align data from multiple lanes
Supports Auto-Negotiation (AN) and Link Training (LT)
Supports Synchronous Ethernet (Sync-E) by providing a clock data recovery (CDR) output signal to the device fabric
Optional per-packet disabling of this feature; RX CRC checking and error reporting
Avalon-ST datapath interface connects the MAC to client logic with the start of frame in the most significant byte (MSB) in MAC+PCS variations
MII datapath interface connects the PCS to client logic in PCS-only variations
TX automatic frame padding to meet the 64-byte minimum Ethernet frame length on the Ethernet link
Avalon Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers

Offering Brief

Device Family	Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Development Language	Encrypted Verilog