Altera offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet FPGA IP core targeted to network infrastructure and data centers. The Low Latency 100G Ethernet FPGA IP core is compliant with the IEEE 802.3ba-2010 Standard. It includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional Forward Error Correction (FEC) block. It also includes IEEE 1588v2 timestamping support and the capability to drive backplanes on supported Stratix and Arria FPGAs. This IP can be used for chip-to-chip interfaces using copper interconnect or optical transceiver modules. The IP core is designed to the IEEE 802.3ba-2010 High-Speed Ethernet Standard, available on the IEEE website (www.ieee.org). The MAC provides cut-through frame processing to optimize latency, supports full wire line speed with a 64-byte frame length, and supports back-to-back or mixed length traffic with no dr...
Altera offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet FPGA IP core targeted to network infrastructure and data centers. The Low Latency 100G Ethernet FPGA IP core is compliant with the IEEE 802.3ba-2010 Standard. It includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional Forward Error Correction (FEC) block. It also includes IEEE 1588v2 timestamping support and the capability to drive backplanes on supported Stratix and Arria FPGAs. This IP can be used for chip-to-chip interfaces using copper interconnect or optical transceiver modules. The IP core is designed to the IEEE 802.3ba-2010 High-Speed Ethernet Standard, available on the IEEE website (www.ieee.org). The MAC provides cut-through frame processing to optimize latency, supports full wire line speed with a 64-byte frame length, and supports back-to-back or mixed length traffic with no dropped packets. All Low Latency 100G Ethernet IP core variations include full-duplex MAC and PHY components.