Compute Express Link (CXL) IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

Known as the industry's first FPGA-based hardened CXL IP solution for Type 1, 2, and 3 devices, Altera's CXL IP is designed to provide the added memory bandwidth and capacity, and acceleration needed for a wide range of data-intensive workloads.

Accelerated Computing: CXL seamlessly connects FPGAs to accelerators and GPUs, enhancing performance in compute-intensive workloads like AI inferencing, high-performance computing, and in-memory databases.

Memory Expansion: CXL enables FPGA-based systems to extend their memory capacity by connecting to CXL-compatible memory devices, improving performance in tiered paging for LLMs, databases, analytics, and large-scale data processing.

Data Processing: FPGAs with CXL support are used in data processing workloads, including real-time data analytics, financial modeling, and high-frequency trading, where low latency and high bandwidth are critical.

Contact Now

Contact Altera

LeadSource

ASAP Account ID

Record Type Name

Key Features

Fully integrated CXL IP solution with PCIe 5.0 x16 (32 GT/s) performance.
CXL 2.0/1.1 compliant IP that combines both hard and soft resources.
R-Tile Hard IP (PHY IP) reduces logic resourcing and simplifies timing closure.
Soft wrapper for added design flexibility and easy integration.
Validated with 4th, 5th, and 6th Gen Intel® Xeon® Scalable Processors.
Compute Express Link Consortium compatible with CXL certification software (CXL_CV_app).
CXL protocol support: CXL.io, CXL.mem, CXL.cache.
Device type support: Type 1, 2, and 3.
CXL 2.0 IP enhanced with 2.0 features and functionality.
Flexible device-attached memory subsystem architecture.
Allows FPGA developers to mix and manage different memory types for maximum scalability and application fit.

Offering Brief

Device Family	Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	Yes
Compliance Link	Compliance Link
Development Language	Encrypted Verilog

Encrypted Verilog Source Code

Design Example(s)

Simulation Models

IP Evaluation Mode (no .sof / .pof generation) - contact your local sales representative for more information regarding CXL IP licensing options

Documentation: IP User Guide, Design Example User Guide - contact your local sales representative for more information regarding the CXL IP User Guide and Design Example User Guide