P-Tile PCIe* Hard IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

P-Tile is an FPGA companion tile available in Stratix® 10 DX and Agilex™ 7 FPGA F-Series devices that support PCIe* configurations up to PCIe 4.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass Modes. PCIe 3.0 and 4.0 configurations are natively supported.

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Key Features

Complete PCIe Protocol Stack in Hard IP – Full implementation of Transaction, Data Link, and Physical Layers with PIPE mode support.
Broad PCIe Version Support – Native PCIe 4.0/3.0 with seamless down-training to 2.0/1.0.
Flexible Port & Mode Options – Root Port, Endpoint, TL-Bypass, SR-IOV (8 PFs, 2K VFs), and bifurcation support.
High Performance Data Handling – Up to 512B Maximum Payload Size (MPS), 4KB Maximum Read Request Size (MRRS), and extended 10-bit tag support for hundreds of outstanding transactions.
Versatile User Interfaces – Avalon-ST, AVMM, segmented packet interfaces, and support for simultaneous TLP handling.
Configuration & Partial Reconfiguration Over PCIe – Supports CVP Init / Update and Partial Reconfiguration (PR) over PCIe link.
Robust System Integration – Supports multiple clocking modes (Common/Independent Reference Clock (refclk) with and without Spread Spectrum SRIS, SRNS), Precision Time Management (PTM), and power states (D0/D3).
Enhanced Reliability & Debug – Advanced Error Reporting, Debug toolkit: detailed protocol/link status, PMA register access, and eye viewing capability.
Complementary IP Ecosystem – Seamless integration with PCIe Scalable Switch IP and MCDMA IP (Avalon-ST, Avalon-MM interfaces).
Comprehensive Software Support – Ready-to-use Linux device drivers, plus Windows device drivers (Stratix 10 only) via Jungo partner for faster deployment.

Offering Brief

Device Family	Agilex® 7 FPGAs and SoC FPGAs F-Series, Stratix® 10 DX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	Yes
Compliance Link	Compliance Link
Development Language	Encrypted Verilog