Scalable Switch IP for PCI Express

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

The Scalable Switch IP delivers high performance, scalability, and flexibility for a variety of systems. Supporting PCIe 3.0, 4.0, and 5.0 with up to x16 lane widths, this switch implements one fully configurable upstream port and connectivity for up to 96 downstream ports. Covering a host of features ranging from virtualization to standard-based routing, this Switch IP is available on Agilex 7 and Stratix 10 DX devices with clocking supporting up to 500 MHz.

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Key Features

Broad PCIe Generation Support: Configurations - PCIe 3.0, 4.0, 5.0 x4/x8/x16 lane configurations
High Port Scalability: Single upstream port with support for up to 96 downstream embedded endpoints or 32 discrete endpoints
Rich Virtualization Capability: Up to 96 PFs and 2048 VFs
Advanced Interrupt Handling: Full support for MSI/MSI-X interrupts for efficient data movement
Robust Error and Reset Management
Standards-Based Routing and Access / Address Services
Hot-Plug Support
VirtIO Capabilities: Support for virtualization and cloud-native workloads
High Throughput Architecture: User packet interface with separate header, data, and prefix
Performance- Tuned Clocking: Core clocking frequency up to 500 MHz for Agilex 7 and 400 MHz for Stratix 10 DX
Support for Agilex 7 FPGAs and SoCs and P-Tile based devices: Stratix 10 DX FPGAs and SoCs

Offering Brief

Device Family	Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Stratix® 10 DX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Development Language	Encrypted Verilog

Encrypted Verilog Source Code

Design Example(s)

Simulation Models

IP Evaluation Mode

Documentation: IP User Guide, Design Example User Guide, IP Release Notes - contact your local sales representative for more information regarding the full versions of the Scalable Switch IP User Guide and Design Example User Guide