L/H-Tile PCIe* Hard IP Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets Altera L/H-Tile are each an FPGA companion tile in Stratix® 10 FPGA devices that support configurations up to PCIe 3.0 x16 in Endpoint (EP) and Root Port (RP) modes. Additionally, H-Tile includes support for SR-IOV functionality. Contact Now Contact Altera X You must have JavaScript enabled to use this form. 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LeadSource - None -Market Place ASAP Account ID Record Type Name Leave this field blank Key Features Complete PCIe Protocol Stack in Hard IP – Full implementation of Transaction, Data Link, and Physical Layers with up to PCIe 3.0 lane rates. Flexible User Interfaces – Avalon® Streaming and Avalon® Memory-Mapped. Multiple Mode Options – Root Port, Endpoint, and SR-IOV (4 PFs, 2K VFs - H-Tile only). Seamless Integration Options – Instantiable from Quartus® Prime Pro Edition IP Catalog or as part of a Platform Designer system, with dynamic design example generation. SR-IOV Features – AER, ATS, TPH, Control Shadow Interface for VF Control Register Fields, FLR and MSI-X for PFs/VFs, and MSI for VFs. Configuration & PHY Simulation Support – Supports CVP Init/Update, PIPE or serial PHY interface simulation, and Avery BFM support for PCIe 3.0 x16 simulation. Clocking Integration – Supports multiple clocking modes (Reference Clock (refclk) with SRNS, but not SRIS). Enhanced Reliability & Debug – Advanced Error Reporting for PFs, PCIe Link Inspector toolkit: LTSSM monitoring, read/write access to PCIe Configuration Space Registers, and PCS and PMA registers. Complementary IP Ecosystem – Seamless integration with Avalon® Memory-Mapped (AVMM) and Multichannel DMA IP. Comprehensive Software Support – Ready-to-use Linux device drivers, plus Windows device drivers via Jungo partner for faster deployment. Offering Brief Offering Brief Device Family Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA Offering Status Production Integrated Testbench Yes Evaluation License Yes Design Examples Available Yes Demo No Compliance Yes Compliance Link Compliance Link Development Language Encrypted Verilog What’s Included? Encrypted Verilog Source Code Design Example(s) Simulation Models IP Evaluation Mode Documentation: IP User Guides, Design Example User Guides, IP Release Notes Ordering Information No license required from Delivered with Quartus Documentation & Resources L/H-Tile Transceiver PHY PCIe User Guide L/H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) IP for PCIe User Guide L/H-Tile Avalon® Memory-Mapped IP for PCIe User Guide Avalon® Memory-Mapped (AVMM) Bridge and Multichannel DMA IP IP Release Notes AN-811: Using the Avery BFM for PCIe 3.0 x16 Simulation on Stratix® 10 Devices See More Documents See Less Documents Market Segment and Sub-Segments Aerospace View Sub-Segments Aerospace Aerospace Back to Market ASIC Proto View Sub-Segments ASIC Proto ASIC Emulation ASIC Prototyping Back to Market Data Center Cloud (Public, Private, Hybrid) View Sub-Segments Data Center Cloud (Public, Private, Hybrid) AI/HPC Networking Storage Back to Market Data Center OEM (IHV, ISV, SI, VAR) View Sub-Segments Data Center OEM (IHV, ISV, SI, VAR) AI/HPC Networking Storage Back to Market Defense View Sub-Segments Defense MIL COMMS Radar/Ew Back to Market Government View Sub-Segments Government Govt Infrastructure Back to Market Industrial View Sub-Segments Industrial Industrial / Manufacturing Robotics Back to Market Medical View Sub-Segments Medical Imaging Video Back to Market Image Test View Sub-Segments Test ATE Communication Tester Other Test RF Instrumentation Back to Market Wireless View Sub-Segments Wireless 5G/ 6G Radio Baseband Back to Market Offering Types and Sub-Types Intellectual Property (IP) Interfaces PCI Express