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EtherCAT MASTER IP

NDR Co.,LTD.

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The EtherCAT Master IP is a high-performance IP for SoC FPGAs that significantly reduces software load, allowing more users flexible utilization. The FPGA hardware-based communication engine achieves high-speed communication intervals and stable communication cycles, thus reducing the software load. This enables the allocation of more CPU processing resources to applications, and software load fluctuations (including the addition of functions) do not affect communication. Furthermore, the IP format allows for "direct" integration onto your own board.

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Key Features

  • High-Speed EtherCAT Master IP, Reduces CPU load and achieves high-precision control.
  • Supports Altera FPGA, enabling flexible system configuration.
  • Provision of APIs and sample software contributes to shortening development time.
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Offering Brief

Offering Brief

Device Family Cyclone® V SE SoC FPGA, Cyclone® V E FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 3 FPGAs and SoC FPGAs C-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Cyclone® V GX FPGA, Cyclone® V ST SoC FPGA, Cyclone® V GT FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 23.1.1
Development Language C/C++, Encrypted VHDL

Documentation

Sample Project

Ordering Information

N-EMB-800

from NDR

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Market Segment and Sub-Segments

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Industrial

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Industrial

Industrial / Manufacturing

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