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LIN Bus Controller

DCD-SEMI

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DCD believes that even though something may be small or slow, it can still offer maximal efficiency and ultimate reliability. That’s why our DLIN controller with UART half-duplex enhanced functionality supports transmission speeds between 1kb/s and 20kb/s, which allows us to transmit and receive LIN messages compatible to: LIN 1.3, LIN 2.1 and the newest LIN 2.2A This interface is a serial communication protocol, primarily designed to be used in automotive applications. Compared to the CAN, The LIN is slower, but thanks to its simplicity, it is much more cost-effective. Our Core is ideal for communication in intelligent sensors and actuators, where the bandwidth and versatility of the CAN is not required. The DLIN core provides an interface between a microprocessor/microcontroller and a LIN bus. It can work as a master or slave LIN node, depending on a work mode determined by the microprocessor/microcontroller. The reported information status includes the type...

DCD believes that even though something may be small or slow, it can still offer maximal efficiency and ultimate reliability. That’s why our DLIN controller with UART half-duplex enhanced functionality supports transmission speeds between 1kb/s and 20kb/s, which allows us to transmit and receive LIN messages compatible to: LIN 1.3, LIN 2.1 and the newest LIN 2.2A This interface is a serial communication protocol, primarily designed to be used in automotive applications. Compared to the CAN, The LIN is slower, but thanks to its simplicity, it is much more cost-effective. Our Core is ideal for communication in intelligent sensors and actuators, where the bandwidth and versatility of the CAN is not required. The DLIN core provides an interface between a microprocessor/microcontroller and a LIN bus. It can work as a master or slave LIN node, depending on a work mode determined by the microprocessor/microcontroller. The reported information status includes the type and condition of transfer operations performed by the DLIN, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). Our Core includes a programmable timer that allows for detecting timeout and synchronization errors. The DLIN is described at the RTL level, empowering the target use in FPGA and ASIC technologies.

The IP core is available in two versions – Basic and Safety-Enhanced.

This sophisticated solution’s been developed as ISO26262-10 Safety Element out of Context. It can optionally be improved by necessary safety mechanisms and provide detailed safety documentation: all ISO26262 soft IP SEooC required work products, which include complete Failure Modes Effects and Detection Analysis FMEDA analysis with step-by-step instruction to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis. All the safety-related work products were checked by a third-party, independent audit.

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Key Features

  • Available in two versions – Basic and Safety-Enhanced
  • Conforms with LIN 1.3
  • LIN 2.1 and LIN 2.2A specification
  • UART half-duplex functionality (available only in basic version)
  • Automatic LIN Header handling
  • Automatic Re-synchronization
  • Data rate between 1Kbit/s and 20 Kbit/s
  • Master and Slave work mode
  • Time-out detection
  • Extended error detection
  • “Break-in-data” support
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Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Cyclone® III FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Cyclone® IV E FPGA, Stratix® III FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 25.1.1
Development Language Encrypted Verilog, Verilog

HDL Source Code

Testbench environment - automatic simulation macros

tests with reference responses

Synthesis scripts

Technical documentation

12 months of technical support

Ordering Information

DLIN

from Direct

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Documentation & Resources

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