CoaXPress-over-Fiber Bridge Host IP core

Overview Key Features Offering Brief What's Included Ordering Information Markets

The CoaXPress-over-Fiber Host Bridge IP Core allows to connect a CoaXPress Host IP Core to an nGMII (10/25 Gbps Media Independent Interface) bus inside an FPGA. nGMII, as defined in IEEE Std 802.3 Clause 46, is the main access to the 10/25G Ethernet physical layer. Delivered as working reference design (when licensed with the S2I CoaXPress Host IP Core) and extensive simulation testbench

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Key Features

Extension for CoaXPress 2.1 compliant IP for host/receiver applications
Support of multiple connections
Speed support up to 100Gbps

Offering Brief

Device Family	Arria® 10 GX FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	No
Design Examples Available	Yes
Demo	No
Compliance	Yes
Intertop	JIIA Compliance Test
Latest Quartus Version Supported	24.3.1
Development Language	Encrypted VHDL, VHDL

Reference Design for Altera Evaluation Kit

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