partner-offering-banner.png

Ultra-high-throughput WiFi LDPC Decoder

XCEL ASICs LLC

Select

This optimized silicon IP core is designed for IEEE 802.11 n/ac/ax/be (WiFi 4/5/6/7) compliant low-density parity-check (LDPC) decoding, addressing the growing demand for ultra-high-throughput solutions in WiFi transceiver chips with a minimal area footprint. The IP core can meet the stringent 30 Gbps throughput requirements of the latest WiFi 7 (IEEE 802.11be) standard. A cross-layer optimization of algorithm, architecture, and circuit has resulted in the best-reported power, performance, and area results for a WiFi-compliant LDPC decoder. Key features of the IP are:

1. Fully compliant with IEEE 802.11n/ac/ax/be (WiFi 4/5/6/7), 2. Achieves the best-reported power, performance, and area results, 3. Implements layered LDPC decoding for faster convergence, 4. Supports all WiFi code rates; 1/2, 2/3, 3/4, 5/6, 5. Supports all WiFi frame lengths: 648, 1296, 1944, 6. Has configurable max-iterations input.

View Partner Website Right arrow Right arrow Partner Product Page Right arrow Right arrow Contact Now

Key Features

  • Fully compliant with IEEE 802.11n/ac/ax/be (WiFi 4/5/6/7).
  • Achieves the best-reported power, performance, and area results.
  • Implements layered LDPC decoding for faster convergence.
  • Supports all WiFi code rates; 1/2, 2/3, 3/4, 5/6.
  • Supports all WiFi frame lengths: 648, 1296, 1944.
  • Has configurable max-iterations input.
Expand Close
Keyfeatures main image

Offering Brief

Offering Brief

Device Family Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Stratix® 10 AX FPGA, Stratix® 10 Bare Die, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Latest Quartus Version Supported 24.1.0
Development Language C/C++, Encrypted Verilog, Verilog

Synthesizable Verilog or SystemVerilog RTL code

FPGA bitstream with implementation reports (timing, resource utilization, etc.)

Synthesized or placed-and-routed netlist (for ASIC or FPGA)

Testbench with representative test vectors and reference outputs

Full BER/BLER curves across SNR, frame lengths, and code rates

Bit-accurate simulation models (C/MATLAB)

Ordering Information

dec-ldpc-wifi

from Direct

Order Now

Market Segment and Sub-Segments

ASIC-Proto-252x228.png

ASIC Proto

View Sub-Segments

ASIC Proto

ASIC Emulation

ASIC Prototyping

Back to Market
MMW.png

Wireless

View Sub-Segments

Wireless

5G/ 6G Radio

Baseband

NTN/Fixed Wireless

Back to Market