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syn1588® Clock_M

The syn1588® Clock_M IP core family provides highly accurate IEEE1588 compliant clock synchronization functions. The syn1588® Clock_M IP cores are suited for direct integration to an Ethernet MAC. Either one or up to four network interfaces can be connected. A large variety of network line speeds are supported. There is an AXI4 Lite CPU interface for communication with the host processor executing the PTP Stack.

The syn1588® Clock_M IP core family offer all functions required to implement a high-accuracy PTP node. The feature-rich architecture allows creating of PTP slave and PTP master nodes. It's sophisticated hardware clock architecture allow fine-grained clock servo control. All published IEEE1588 standards are supported.

A typical application example is the syn1588® PCIe NIC. This standard PCIe Ethernet network interface card is made up of a single FPGA that includes the syn1588® Clock_M IP core as well as the Ethernet MAC and the PCIe interface.

The syn1588® Clock_M IP core family provides highly accurate IEEE1588 compliant clock synchronization functions. The syn1588® Clock_M IP cores are suited for direct integration to an Ethernet MAC. Either one or up to four network interfaces can be connected. A large variety of network line speeds are supported. There is an AXI4 Lite CPU interface for communication with the host processor executing the PTP Stack.

The syn1588® Clock_M IP core family offer all functions required to implement a high-accuracy PTP node. The feature-rich architecture allows creating of PTP slave and PTP master nodes. It's sophisticated hardware clock architecture allow fine-grained clock servo control. All published IEEE1588 standards are supported.

A typical application example is the syn1588® PCIe NIC. This standard PCIe Ethernet network interface card is made up of a single FPGA that includes the syn1588® Clock_M IP core as well as the Ethernet MAC and the PCIe interface.

Key Features

  • High Accuracy clock synchronization
  • Timestamp hardware event signals - EVENT function
  • Generate on-time hardware events (signals) - TRIGGER function
  • Generate peridical hardware signsls (clocks) - PERIOD function
  • Generate and read IRIG-B data stream
  • 1PPS In/Out
  • Linux and Windows driver optionally available
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Offering Brief

Offering Brief

Device Family Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V E FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available Yes
Demo Yes
Compliance No
Intertop IEEE1588ISPCS Plug Fests attended since 15+ years now
Latest Quartus Version Supported 25.1.0
OS Support Linux,Windows
Development Language Encrypted VHDL, VHDL

IP core, Support, syn1588® Software suite (different Licensing options)

Ordering Information

Market Segment and Sub-Segments