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10G Ethernet MAC IP

Qbit Labs Incorporation

Member

The 10G Ethernet MAC (Media Access Control) IP Core is a high-performance, configurable solution designed to facilitate seamless and reliable data communication over 10 Gigabit Ethernet networks.

Compliant with IEEE 802.3ae standards, our 10G MAC core is optimized for low-latency, high-throughput applications across networking, telecom, data center, and enterprise systems.

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Key Features

  • IEEE 802.3ae Compliant: Fully compliant with the 10G Ethernet standard, ensuring seamless interoperability with industry-standard devices
  • 10 Gbps Full-Duplex Support: High-performance operation at full line rate for demanding data transfer applications.
  • VLAN Tagging (IEEE 802.1Q): Enables traffic prioritization and virtual network segmentation.
  • XGMII and AXI/AXIS Interfaces: Supports XGMII for PHY connectivity and optional AXI/AXIS interfaces for integration with standard bus systems.
  • Pause Frame (IEEE 802.3x) Support: Implements flow control via pause frame generation and processing for congestion management.
  • FPGA/ASIC Ready: Fully synthesizable RTL with options for encryption or soft delivery; validated on major FPGA platforms
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Offering Brief

Offering Brief

Device Family Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® IV GX FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog

Synthesizable RTL source code

Directed/random/constrained-random sequences covering LTSSM, configuration, link training, FLIT mode, error injection (FEC/CRC scenarios), power states, reset

Embedded firmware / low-level SW

Software integration guide

Full design documentation

Ordering Information

QBL-IP-Ethernet-10G

from Direct

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