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NVMe Controller (Silicon Proven IP for Altera Devices)

The NVMe Controller is a configurable and UNH-certified solution for enterprise and client PCIe SSDs, featuring multi-core and lock-free architecture. It includes NVMe-aware DMA engines, firmware-controlled command handling, and supports AXI and proprietary interfaces. Integrated with Mobiveil’s GPEX or third-party NAND controllers, it achieves optimized latency, throughput, and efficiency.

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O-RAN FPGA IP

Altera O-RAN IP delivers a flexible, standards-compliant fronthaul interface for 5G and LTE systems using the 7-2x functional split. Supporting both control and user planes per O-RAN-FH.CUS.0-v03.00, it simplifies DU-RU integration, accelerates development, and ensures interoperability in disaggregated, open RAN architectures.

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PCI-M32: 32-bit, 33 MHz PCI Master/Target

The PCI-M32 implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz PCI clock.

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PCI-M32MF 32-bit/33MHz Multi-Function PCI Master/Target

The PCI-M32MF is a PCI 2.3-compliant master/target core supporting a 32-bit address/data bus at up to 33 MHz. It enables 1 to 8 independent PCI functions per chip, each with 64–256 bytes of Configuration Space and up to six Base Address Registers, supporting I/O and Memory decoding from 16 bytes to 4 GB. Backed by over 20 years of CAST PCI IP expertise, the core is designed for easy reuse and integration, and is available as synthesizable RTL or FPGA netlist with comprehensive deliverables.

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PCI-T32: 32-bit/33MHz PCI Target

The PCI-T32 is a 32-bit target PCI interface core compliant with PCI 2.3, operating at up to 33 MHz. It includes 64 bytes of PCI Configuration Space, expandable to 256 bytes, and supports six Base Address Registers for I/O or Memory decoding from 16 bytes to 4 GB. Supported commands include Configuration, Memory, and I/O Reads/Writes, as well as MRM, MRL, and MWI. Built on over 15 years of CAST PCI IP experience, the core is designed for easy reuse and integration. It is available in synthesizable RTL or as an FPGA netlist, with full integration support.

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PCI-T32MF: 32-bit, 33 MHz Multifunction Target Interface Core

The PCI-T32MF is a target-only PCI interface core compliant with the PCI 2.3 specification, supporting a 32-bit address/data bus and operating at up to 33 MHz. It allows one to eight independent PCI functions per chip, each with 64 to 256 bytes of PCI Configuration Space and up to six Base Address Registers, decoding I/O and Memory space from 16 bytes to 4GB. Developed with over 20 years of CAST PCI IP expertise, the core is optimized for easy reuse, integration, and technology mapping. It is available as synthesizable RTL or a targeted FPGA netlist, with full support for rapid implementation.

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PCIe GEN6 Controller IP

The PCIe Gen 6 Controller IP supports the full PCI Express 6.x specification, offering scalable, high-speed communication for enterprise-grade solutions. FIRST in the industry to deliver PCIe IPs across multiple generations. It is: - Optimized for existing and emerging FPGA uses cases for hardening onto ASIC / SoC. - Best for large memory, compute-intensive and high data rate applications.

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PCIe GEN6 PHY IP

Logic Fruit's PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for high-speed data transfer. It supports advanced applications, including AI/ML, High-Performance Computing, and next-generation storage solutions.

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PIB

PIB is an intelligent development platform based on an Intel x86 i7 CPU and Cyclone V GT FPGA, designed for applications such as industrial control, vision optimization, and edge computing.

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Listing 9 out of 311 Offerings