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CoaXPress-over-Fiber Bridge Device IP core

Bridge IP Core for CoaXPress protocol to use Ethernet physical layer for data transfer.

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CoaXPress-over-Fiber Bridge Host IP core

Bridge IP Core for CoaXPress protocol to use Ethernet physical layer for data transfer.

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Comet A65 SOM

The Comet A65 SOM is a high-performance System-On-Module powered by Altera’s largest Agilex™ 5 SoC FPGA, designed for demanding industrial edge applications.

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Comet A65 SOM

The Comet A65 SOM is Terasic’s production-ready System-on-Module built on Altera’s largest Agilex® 5 SoC FPGA (656K LEs). With integrated HPS/ARM, 12GB LPDDR4, and high-speed expansion connectors, it delivers a powerful, scalable platform for industrial edge applications — from robotics to medical imaging — all with a free Altera® Quartus® Pro Edition license included.

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Compact Ethernet TSN Switch 10M/100M/1G/2.5G

Comcores' compact 10M–2.5G TSN Switch IP targets automotive, avionics, and industrial use, offering IEEE TSN compliance, cut-through switching, and the lowest market gate count, with MAC learning, VLAN 802.1Q, multicast, and 802.1AS timing support.

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Compute Express Link (CXL) IP

CXL IP is designed to provide the added memory bandwidth and capacity, and acceleration needed for a wide range of data-intensive workloads.

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Consulting for electrical characteristics of printed circuit boards

For signal transmission and noise problems in the development of electronic devices, especially those using Altera FPGA-based boards, we utilize our proprietary electronic measuring instruments and simulation software to identify issues and propose effective improvements.

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Cortex-A53 Software Development

Agilex™ 7 and Agilex™ 9 SoC implements Armv8.0 architecture which has many benefits. The training covers all new architecture features, guide engineers how to utilize the new features and optimize performance, code density, power consumption, and debug. Extensive hands-on labs to practice all necessary aspects of the CPU.

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Cortex-A55 Software Development

Agilex™ 5 HPS gets significant uplift, versus the prior architectures with dual Cortex-A76 plus dual Cortex-A55 plus DynamIQ Shared Unit (DSU) that forms the upgraded MPU architecture.Upgraded Application Processor Subsystem (APS). New Cache Coherency Unit (CCU), Generic Interrupt Controller (GIC), System Memory Management Unit (SMMU), and On-Chip RAM (OCRAM) that supports the new architecture

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Showing 199-207 of 896 Offerings