banner

Find Offerings

Switch to Partners

By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by

Loading

By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by

CCSDS SCCC Turbo Encoder and Decoder

The Creonic CCSDS SCCC Turbo IP core the ideal fit for further applications where high throughput and high spectral efficiency is key for operation.

CDC - Customizable Display Controller IP Core Family

Highly customizable MIPI-DPI compliant display controller supporting on-the-fly image composition from several input sources (images in memory or AXI4 Stream) with a powerful set of image processing features.

Offerings Image

ChaCha20-Poly1305 IP core

ChaCha20-Poly1305 IP core implements the ChaCha20 stream cipher together with the Poly1305 message authentication code (MAC), following the IETF standard for Authenticated Encryption with Associated Data (AEAD).

ChevinID

ChevinID is a silicon‑rooted authentication and protection solution designed to secure FPGA, ASIC, and embedded systems across the entire lifecycle. Built on Physically Unclonable Function (PUF) technology, ChevinID assigns each device a unique, intrinsic identity that cannot be copied or transferred, enabling strong, hardware‑level trust without external secure elements. The solution protects valuable intellectual property—including FPGA bitstreams, RTL designs, and embedded software—by binding execution and access to authenticated hardware. Cryptographic keys are securely contained within encrypted envelopes, ensuring they are never exposed during operation. This approach safeguards against cloning, reverse engineering, and unauthorized deployment. ChevinID also enables flexible, hardware‑based licensing models, allowing vendors to control feature activation, enforce usage policies, and create new revenue streams. For Intel/Altera FPGA users, ChevinID integrates seamlessly with exist

CIC FPGA IP Core

The CIC FPGA IP core offers computationally efficient cores for extracting baseband signals.

Offerings Image

CLARE

CLARE is a hypervisor-centric software stack to simplify the development of next-generation cyber-physical systems using heterogeneous computing platforms and offering a ready-to-use environment for deploying mixed-criticality applications.

Clock to PPS

Clock to Pulse Per Second Converter

CoaXPress Device IP Core

IP Core for CoaXPress camera applications with speed support from 1 Gbps up to 100 Gbps.

CoaXPress Host IP Core

IP Core for CoaXPress host/receiver applications with speed support from 1 Gbps up to 100 Gbps.