banner

Find Offerings

Switch to Partners

By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by
By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by
Offerings Image

TSN-EP: TSN Ethernet Endpoint Controller

The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS-2020) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC. Enhanced reliability features can also be sup ported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci).

View Details Right arrow Right arrow
/
Offerings Image

TSN-SE: TSN Ethernet Switched Endpoint Controller

"The TSN-SE is a highly configurable two-port Switched Endpoint Controller IP core tailored for Time-Sensitive Networking (TSN) Ethernet systems. It embeds hardware support for 802.1AS-2020 timing synchronization, 802.1Qav/Qbv traffic shaping, 802.1Qbu/802.3br frame preemption, plus two low-latency Ethernet MACs. Optional modules enable enhanced reliability with 802.1CB frame replication and elimination, and 802.1Qci per-stream filtering and policing. Designed for daisy-chained or ring topologies and bridged endpoints, TSN-SE delivers precise, deterministic ingress/egress latency via cut-through switching and minimal buffering, simplifying time-aware application development. It provides real-time timing data timestamps, alarms, and allows dynamic traffic-shaping configuration. Integration is seamless via standard AMBA® interfaces: a 32-bit APB bus for control/status, and 32-bit AXI-Streaming for packet I/O. Optional DMA engine and software stacks are also available.

View Details Right arrow Right arrow
/
Offerings Image

TSN-SW: TSN Ethernet Switch

The TSN-SW implements a highly flexible, low-latency, multiport TSN Ethernet switch. It supports the hardware functionality for Ethernet bridging according to the IEEE 802.1Q standard and implements the essential TSN timing synchronization and traffic-shaping protocols (i.e. IEEE 802.1AS-2020, 802.1Qav, 802.1Qbv, and 802.1Qbu, 802.1br). Enhanced reliability features can also be supported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci). Featuring a configurable number of ports, the Layer-2 switch operates in cut-through mode at wire speed and can provide sub-microsecond port-to-port latency. The core is hence suitable for applications with demanding real-time requirements.

View Details Right arrow Right arrow
/

TSoM

TSoM is a pocket-sized module powered by the latest Intel Cyclone® V SoC FPGA. The board itself takes advantage of the ARM dual-core Cortex-A9 CPU and 110K FPGA Logic Elements to achieve lowest system cost and power efficiency. Armed with 1GB DDR3 memory for FPGA and HPS fabric respectively, and up to 8GB eMMC flash, the Cyclone V module ideally suited for building high bandwidth and large capacity memory system for a wide range of embedded applications.

View Details Right arrow Right arrow
/

Turbo-V FPGA IP Core

Turbo codes assist in forward error correction systems. You can use Turbo codes in other applications that require reliable information transfer over bandwidth- or latency-constrained communication links in the presence of data-corrupting noise.

View Details Right arrow Right arrow
Altera logo

UDPIP-100G: 100G UDP/IP Hardware Protocol Stack

Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 100 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.

View Details Right arrow Right arrow
/

UDPIP-1G: UDP/IP Hardware Protocol Stack

Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 10 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.

View Details Right arrow Right arrow
/

UDPIP-40G/50G: 40G/50G UDP/IP Hardware Protocol Stack

Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 50 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.

View Details Right arrow Right arrow
/

USB 10Gbps Device Controller (USB32SF)

10Gbps Device IP Core

View Details Right arrow Right arrow
/
Listing 9 out of 320 Offerings