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EtherCAT MASTER IP

NDR has acquired the technology of EtherCAT Hardware Master owned by a major industrial machinery manufacturer, and developed a SoC FPGA IP so that more users can flexibly use it. The FPGA hardware communication engine reduces the software load by providing a fast communication interval and stable communication cycle. The resources required for CPU processing can be allocated to applications and hence the software load fluctuations (including the addition of functions) will not affect the communication. In addition, it is also possible to mount directly to the proprietary boards using the IP.

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EtherCAT Slave Subsystem for Altera FPGA

EtherCAT Slave for Altera FPGA provides an optimized EtherCAT IP Core and a Communication Processor for the Integration of EtherCAT and other industrial networks into field devices. It uses the same API for all supported protocols.

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Ethernet MAC 10M/100M/1G/2.5G

Comcores' 10M–2.5G Ethernet MAC IP enables IEEE 802.3-compliant data communication for switches and routers, featuring AXI-S client interface and GMII/RGMII/MII PHY interfaces. It is compact, low-latency, highly configurable, silicon-agnostic (ASIC/FPGA), and optionally supports IEEE 1588 timestamping.

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EtherNet/IP Adapter Subsystem for Altera FPGA

EtherNet/IP Adapter for Altera FPGA provides an optimized Switch IP Core and a Communication Processor for the Integration of EtherNet/IP and other industrial networks into field devices. It uses the same API for all supported protocols.

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EVALUATION AS A SERVICE WHITE BOX

Risk assessment is one of the most important stages during a design development.

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Everspin MRAM "Cruvi" xSPI daughter card with EM064LX

MRAM daughter card with a Cruvi high speed connector based on the Trenz platforms.

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exFAT IP for CPU less NVMe IP

exFAT IP for NVMe is designed to integrate with DG NVMe IP and the Avalon-ST Hard IP for PCIe (the PCIe Hard IP in Altera FPGA devices). This IP core provides an ideal solution for accessing NVMe devices using the exFAT file system with high-speed performance, comparable to raw data access.

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F-Tile PCIe Hard IP

F-Tile is an FPGA companion tile that supports PCI Express* configurations up to PCIe 4.0 x16 in Endpoint (EP), Root Port (RP) and Transaction Layer (TL) Bypass modes. PCIe 3.0 and 4.0 configurations are natively supported.

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F3076X 400G Data Processing Unit (DPU)

The Napatech DPU F3076X is a 400G PCIe Gen5 card with an Agilex™ AGI041 FPGA and a Xeon® 6 32-core SoC.

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Showing 352-360 of 896 Offerings