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UVM training

The Universion Verification Method (UVM) is the leading verification framework for digital design. Our UVM training offering teaches all aspects of the UVM framework, how it works, and how to apply it in your designs. It is configurable to include the necessary knowledge on Verilog and SystemVerilog that is used as the basis.

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VHDL training

For more than 20 years we provide the best classroom training on VHDL in the Benelux. Our Professional VHDL training gives a very good foundation for professionals who want to start with VHDL. For the more advanced topics we have our Advanced VHDL training that will discuss advanced cases to bring your VHDL knowledge to the next level.

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Video and Vision Processing Suite

The Altera FPGA Video and Vision Processing Suite is a collection of next-generation Altera intellectual property (IP) functions that you can use to facilitate the development of custom video and image processing designs.

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Virtualyzr™ Pre-Silicon Verification (HW)

The Virtualyzr Side Channel Analysis license enables security evaluation of a design implementation at the pre-silicon level, before launching any foundry operation.

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Viterbi IP Core

The Viterbi Intel FPGA IP core generates high-performance, soft-decision Viterbi intellectual property (IP) functions that implement a wide range of standard Viterbi decoders.

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Volitio Cyclone® 10 GX Networking Platform

10G Ethernet capable system designed for Private Island open source project that utilizes the Altera Cyclone 10 GX. This FPGA is a very powerful device that provides 10 Gbps network connectivity using embedded high-speed transceivers. We utilize this high-performance system to develop custom networking and bridging solutions for our customers. Using our in-house manufacturing capabilities, hardware platform can be quickly modified per customer's requirements to include additional memory, transceivers, and other peripherals.

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Warp FPGA IP

The Altera Warp FPGA IP core, part of the Video and Vision Processing (VVP) Suite, delivers a high-performance solution for applying geometric corrections and non-linear transformations to real-time video streams.

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WILDSTAR 3AE1 3U OpenVPX FPGA Processor (WS3AE1)

WS3AE1 3U OpenVPX FPGA Processor is a SOSA™-aligned Direct RF solution that delivers high-performance processing and eight channels each of 64 Gsps ADC and DAC at a 10-bit resolution. It includes up to two Analog Interface Mezzanine Sites. These can be populated with Annapolis or 3rd party/customer-designed RF Cards for front-end personalization (e.g. pre-filtering or analog conditioning) for applications of interest.

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XAUI PHY FPGA IP

The XAUI PHY IFPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Altera FPGA to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module. You can implement the XAUI PHY in hard silicon in Intel's 65 nm and 40 nm FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. In Intel 20 nm and beyond FPGA families, a XAUI PHY can be implemented in soft IP.

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Listing 9 out of 483 Offerings