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HiPrAcc™ NC220 Low Profile PCIe Accelerator Card

Low-profile PCIe accelerator for data centers and edge AI, with up to 400 Gbps Ethernet, x16 PCIe Gen4, Agilex™ 7 FPGAs (006 through 027 density), 24/12 GB DDR4 and SMB PPS sync input

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HiPrAcc™ NCS200 Networked Computational Storage Card

FPGA accelerator card featuring Agilex™ 7 Series FPGA with x16 Gen4 PCIe, 4x 100G networking interfaces, four on-card Gen4 M.2 NVMe SSDs (22110 and 2280) and two DDR4 UDIMM/RDIMM/LRDIMM slots — ideal for SmartNIC, computational storage and signal/image processing.

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HiPrAcc™ NCS280-I CXL/PCIe Gen5 Accelerator 

High performance CxL/PCIe Gen5 accelerator with R-Tile, dual QSFP28 based Ethernet networking, and dual on-card Gen4 M.2 NVMe SSDs

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HMAC-SHA256 accelerator

Chevin Technology’s HMAC‑SHA256 cryptographic accelerator provides fast, secure generation and verification of message authentication codes, enabling trusted communication between senders and receivers. Implemented as an all‑RTL solution, it efficiently computes SHA‑256 hashes and HMAC codes for messages of any length, supporting multiple parallel data streams limited only by available memory. It is ideal for high‑security, high‑throughput applications—such as cybersecurity, defense, and aerospace—where CPU‑based solutions cannot meet performance and security requirements

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HSDLC: HDLC & SDLC Protocol Controller Core

The HSDLC IP core implements HDLC and SDLC protocols, based on the Intel® 8XC152 GSC in SDLC mode with added HDLC and proprietary frame support. It connects as a peripheral to a host processor via APB or 80C51-like interfaces, with full interrupt support for efficient operation. Flexible design allows two independent TX/RX interfaces with support for full- or half-duplex, hardware flow control (RTS/CTS), collision detection, and programmable baud rates. Receive clock is derived from incoming data or supplied externally. Available in Normal and Safety-Enhanced (TMR, DO-254 DAL-A) versions, the HSDLC core is fully synchronous, scan-ready, verified, and delivered in Verilog RTL or FPGA netlist. Deliverables include scripts, testbench, and complete documentation.

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HSMC Video Development, Low Latency Video Up-scaler & Chroma Keyer

HSMC Video Development, Low Latency Video Up-scaler & Chroma Keyer

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HSR & PRP Network Redundancy (IEC62439-3)

Full standalone hardware only solution of a HSR & PRP Network Redundancy Dual Attached Node (DAN) and RedBox

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HTG-AGLX7

The HTG-AGLX-7P platform provides access to large FPGA gate densities, PCIE Express Gen5 connectivity, wide range of I/Os and two expandable DDR4 memory SODDIM sockets for variety of different programmable applications.

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HyperBus Controller (Silicon Proven IP for Altera Devices)

Mobiveil’s HyperBus Controller enables high-speed (up to 333 MB/s) flash access over a 12-pin interface, surpassing legacy SPI/QSPI protocols. It supports AXI interface, 0-wait-state writes, continuous burst reads, and XiP execution. Ideal for HyperFlash/HyperRAM integration, it maximizes throughput and performance in constrained systems.

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Showing 442-450 of 896 Offerings