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KEIm-A5ESoM

The KEIm-A5ESoM is a System-on-Module (SoM) powered by Agilex™ 5 SoC FPGA E-Series. The SoM board is equipped with 4GByte LPDDR4 memory for HPS, dual channels of 4Gbyte LPDDR4 memory, 32GByte eMMC memory for storage, 2Gbit QSPI flash as configuration memory.

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KEIm-A5ESoM Mini

The KEIm-A5ESoM Mini is a System-on-Module (SoM) powered by the Agilex 5 SoC FPGA E-Series. The module features 4GByte of LPDDR4 memory, 32 GByte eMMC storage, and 1 Gbit QSPI flash memory used as the configuration ROM.

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KiviPQC-Box - Post-Quantum Key Encapsulation and Digital Signature IP Core (ML-KEM und ML-DSA)

KiviPQC-Box - Post-Quantum Key Encapsulation and Digital Signature IP Core (ML-KEM und ML-DSA)

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KiviPQC-DSA - Post-Quantum Digital Signature IP Core (ML-DSA)

KiviPQC-DSA - Post-Quantum Digital Signature IP Core (ML-DSA)

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KiviPQC-KEM - Post-Quantum Key Encapsulation IP Core (ML-KEM)

KiviPQC-KEM - Post-Quantum Key Encapsulation IP Core (ML-KEM)

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KJN-XL1_ENC(JPEG)

Our "KJN-XL1_ENC" is a latest JPEG standard, offering a JPEG IP core that achieves both high compression and high image quality.

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KRM-10A9W027

industrial grade SoM based on Agilex™ 9 DirectRF AGRW027R28A2I2V

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L/H-Tile PCIe* Hard IP

L/H-Tile are each an FPGA companion tile that supports PCI Express* configurations up to PCIe 3.0 x16 in Endpoint (EP) and Root Port (RP) modes.

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L8051XC1: Legacy-Configurable 8051-Compatible Microcontroller IP Core

The L8051XC1 is an MCS®51-compatible microcontroller core designed to match the timing and peripherals of legacy 8051-based systems. It supports instruction execution every 12, 6, or 4 clock cycles and includes user-selectable architectural extensions such as multiple data pointers, a multiply/divide unit, and a power management unit. The core can be coupled with peripherals that match the behavior of those from legacy vendors like Intel, NXP, Infineon, Maxim, and TI. Several pre-configured versions are available, along with options for customization. It supports legacy code and modern development through CAST’s on-chip debugging features and compatibility with IAR Embedded Workbench and Keil uVision™ IDEs. With design experience dating back to 1997 and hundreds of 8051 IP customers, CAST ensures that the core is optimized for easy ASIC/FPGA reuse. It is strictly synchronous, with positive-edge clocking and no internal tri-states. At 65nm, the core uses just 7.9K–20K gates.

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Showing 532-540 of 898 Offerings