banner

Find Offerings

Switch to Partners

By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by

Loading

By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by

Lossless Compression IP

Gidel’s lossless compression IP targeting FPGA performs real-time compression for Color Filter Array (CFA – e.g., Bayer), Monochrome, and RGB images and videos. The IP enables compression of multi-camera/sensor inputs at pixel clock rates exceeding 1 gigapixel/s while using very small FPGA resources and minimal power consumption. The compression is highly efficient and, in real-case video applications, has achieved a lossless compression ratio of 1:2.3. The Lossless IP can be embedded seamlessly in Gidel's image acquisition systems, including the Gidel frame grabbers and compact edge computers. The compression supports high-end camera streaming, including 10+ GigE Vision, CoaXPress and Camera Link. Gidel's real-time compression IPs are particularly beneficial for high-bandwidth and high-resolution imaging and vision application enabling increased recording time, reduced storage size, and reduced post recording data offload and compression time on host computer.

View Details Right arrow Right arrow
/

Lossless JPEG-LS Encoder

The JPEGLS-E core from Alma Technologies is an ISO/IEC 14495-1 compliant JPEG-LS encoder that offers a very compact, efficient and high-performance solution for up to 16-bit per component numerically lossless image and video data compression.

View Details Right arrow Right arrow
/
Offerings Image

Lotus Microsystems Thermal Guides

LTG devices from Lotus Microsystems are thermally conductive yet electrically isolated silicon-based thermal jumpers. These devices are designed to guide heat away from hot electronic components, such as between active devices and ground planes, without establishing an electrical connection. LTG devices significantly enhance thermal conductivity, particularly in situations with limited or no direct access to a ground plane or heatsink, such as in a high-side switch in a half-bridge configuration.Silicon, used as an alternative to traditional ceramic materials in the construction of thermal jumpers, offers a cost-effective solution with high thermal conductivity and excellent thermomechanical properties, and is reliably processed. The incorporation of LTG devices improves circuit reliability and reduces the overall cost of the thermal management system. They are available in three standard EIA sizes (0201, 0402, 0603:

View Details Right arrow Right arrow
/

Low Latency Ethernet 100G MAC and PHY FPGA IP

Altera offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet FPGA IP core targeted to network infrastructure and data centers. The Low Latency 100G Ethernet FPGA IP core is compliant with the IEEE 802.3ba-2010 Standard. It includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional forward error correction (FEC) block.

View Details Right arrow Right arrow
Altera logo
Offerings Image

Low Latency Ethernet 10G MAC FPGA IP

The Low Latency Ethernet 10G MAC FPGA IP core offers low round-trip latency and efficient resource footprint. This IP core offers programmability of various features listed. It can be used in conjunction with the Multi-Rate PHY FPGA IP core to support the range of 10M/100M/1G to 10G data rates.

View Details Right arrow Right arrow
Altera logo

Low Profile Arria® 10 GX XpressGXA10-LP1151B PCIe Board

This low-profile PCIe board based on an Intel® Arria® 10 FPGA delivers high bandwidth and ultra-low latency for networking, telecom, and signal processing applications. Featuring QSFP+ connectivity up to 40GbE, it combines compact design, efficient cooling, and easy integration for embedded and server environments.

View Details Right arrow Right arrow
/

Low-Latency 10G Ethernet MAC - MLE FPGA IP Core Design

The 10G Ethernet MAC IP Core from Fraunhofer Heinrich Hertz Institute is a low latency Ethernet Media Access Controller (MAC) according to IEEE802.3 -2008 specification. The IP Core was specifically designed to have the lowest possible latency, and to be as resource efficient as possible at the same time.

View Details Right arrow Right arrow
/

LVDS Tunneling Protocol and Interface IP

LVDS Tunneling Protocol and Interface (LTPI) is a soft IP introduced in the DC-SCM 2.0 specification to facilitate the tunneling of low-speed signals between the host platform module (HPM) and secure control module (SCM) through the low-voltage differential signaling (LVDS) interfaces.

View Details Right arrow Right arrow
Altera logo

LZ4SNP-C: LZ4/Snappy Data Compressor

LZ4SNP-C is a custom hardware implementation of a lossless data compression engine that complies with the LZ4 and Snappy compression standards. The core receives uncompressed input files and produces compressed files. No post-processing of the compressed files is required, as the core encapsulates the compressed data payload with the proper headers and footers.The core’s flexible architecture enables fine-tuning of its compression efficiency and throughput to match the requirements of the end application. More than one block compression engine can be internally instantiated to scale throughput, while block and history window sizes can be adjusted to optimize either hardware resources utilization or compression efficiency.

View Details Right arrow Right arrow
/
Showing 550-558 of 898 Offerings