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Tone Mapping Operator FPGA IP

The Tone Mapping Operator (TMO) FPGA IP corrects poorly exposed images and video to reveal invisible details.

TPC IP

Turbo Product Codes (TPC) are powerful Forward Error Correction (FEC) schemes that offer strong error-correcting capability with moderate complexity. TPCs are widely adopted in satellite communications, deep-space telemetry, aerospace systems, and military-grade networks, where low bit-error rates (BER) and high data integrity are essential under challenging noise conditions.

TR10a-HL Arria® 10 FPGA Development Kit

Terasic TR10a-HL Development Kit provides the ideal hardware solution for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency communication, and power efficiency. With a full-height, 1/2-length form-factor package, the TR10a-HL is designed for the most demanding high-end applications, empowered with the top-of-the-line Altera Arria 10 GX, delivering the best system-level integration and flexibility in the industry.

TR10a-HL2 Arria® 10 FPGA Development Kit

Terasic’s TR10a-HL2 is designed to advance the agility, flexibility and speed and delivers blazing performance in cloud and data center applications.

Transparent Compression

Eideticom’s NoLoad Transparent Compression delivers high-performance inline data compression. Its NVMe-compliant interface ensures native driver support across all CPU platforms and operating systems, including Linux, FreeBSD, and Windows.

Triple-Speed Ethernet FPGA IP

A complete 10/100/1000 Mbps Ethernet IP with flexible IP options including MAC only, PCS only, MAC + PCS, MAC + PCS + PMA, PCS + PMA.

TSN End-Node (IEEE802.1 Time Sensitive Networking End-Node)

Full standalone hardware only solution of a TSN End-Node

TSN Network Node (IEEE802.1 Time Sensitive Networking Switched End-Node)

Full hardware only solution for a TSN Switched End-Node

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TSN-EP: TSN Ethernet Endpoint Controller

The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS-2020) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC. Enhanced reliability features can also be sup ported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci).