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The XAUI PHY IFPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Altera FPGA to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module. You can implement the XAUI PHY in hard silicon in Intel's 65 nm and 40 nm FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. In Intel 20 nm and beyond FPGA families, a XAUI PHY can be implemented in soft IP.
By Altera
Balanced speed AES256-GCM core implements the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM) with few Gpbs linerates.
By Xiphera Ltd.
Extreme speed AES256-GCM core implements the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM) with up to 800G linerate.
High speed AES256-GCM core implements the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM) with few tens of Gpbs linerates.
Xiphera’s Versatile AES IP core implements the Advanced Encryption Standard (AES) with a 256-bit key in five selectable modes: ECB, CBC, CFB, OFB, and CTR.
AES-XTS IP cores implement the Advanced Encryption Standard (AES) with a 256-bit key in XTS mode.
MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model.