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P-Tile PCIe* Hard IP

P-Tile is an FPGA companion tile that supports PCI Express* configurations up to PCIe 4.0 x16 in Endpoint (EP), Root Port (RP) and Transaction Layer (TL) Bypass modes. PCIe 3.0 and 4.0 configurations are natively supported.

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P4 Suite for Altera

The P4 Suite for FPGA is a high-level design tool that enables rapid development of custom networking data plane functionality using the P4 programming language. P4 is an open-source, domain-specific language designed to describe how a packet is processed by a data plane device.

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Packet Switching

We offer UltraEthernet and RoCEv2, GPON, XGS-PON,25G-PON & 50G-PON, Ethernet from 1G to 1.6T PCS/MAC/FEC, Packet Processing, Traffic Managers, 4G & 5G Mobile Front and Backhaul, Sub-nanosecond timestamping, MPLS-TP & Ethernet OAM, IP4&IP6 forwarding, 1588v2 and SYNC-E, Datacenter Offload, 600G FlexEthernet, vEPC, 100G PLE

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Parretto DisplayPort IP Core

The Parretto DisplayPort is a resource optimized DisplayPort v1.4 IP Core solution for FPGA devices. Designed for easy of use, the core is available as both source (DPTX) and sink (DPRX).

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PCB Design Services

PCB design, including supply chain under ODM model, includes complex high-speed systems, RF systems up to 120GHz, and mixed-signal PCBs.

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PCI-M32: 32-bit, 33 MHz PCI Master/Target

The PCI-M32 implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz PCI clock.

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PCI-M32MF 32-bit/33MHz Multi-Function PCI Master/Target

The PCI-M32MF is a PCI 2.3-compliant master/target core supporting a 32-bit address/data bus at up to 33 MHz. It enables 1 to 8 independent PCI functions per chip, each with 64–256 bytes of Configuration Space and up to six Base Address Registers, supporting I/O and Memory decoding from 16 bytes to 4 GB. Backed by over 20 years of CAST PCI IP expertise, the core is designed for easy reuse and integration, and is available as synthesizable RTL or FPGA netlist with comprehensive deliverables.

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PCI-T32: 32-bit/33MHz PCI Target

The PCI-T32 is a 32-bit target PCI interface core compliant with PCI 2.3, operating at up to 33 MHz. It includes 64 bytes of PCI Configuration Space, expandable to 256 bytes, and supports six Base Address Registers for I/O or Memory decoding from 16 bytes to 4 GB. Supported commands include Configuration, Memory, and I/O Reads/Writes, as well as MRM, MRL, and MWI. Built on over 15 years of CAST PCI IP experience, the core is designed for easy reuse and integration. It is available in synthesizable RTL or as an FPGA netlist, with full integration support.

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PCI-T32MF: 32-bit, 33 MHz Multifunction Target Interface Core

The PCI-T32MF is a target-only PCI interface core compliant with the PCI 2.3 specification, supporting a 32-bit address/data bus and operating at up to 33 MHz. It allows one to eight independent PCI functions per chip, each with 64 to 256 bytes of PCI Configuration Space and up to six Base Address Registers, decoding I/O and Memory space from 16 bytes to 4GB. Developed with over 20 years of CAST PCI IP expertise, the core is optimized for easy reuse, integration, and technology mapping. It is available as synthesizable RTL or a targeted FPGA netlist, with full support for rapid implementation.

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