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VOLLO

Ultra-low latency machine learning inference accelerator for latency-critical applications. Runs on Altera Agilex 7 Series FPGAs. Proven over hundreds of thousands of production trading hours in financial trading and also winning in wireless telecoms, network security and defense.

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VPX540

*Utilizing Altera Agilex SoC (AGRM027) with quad Core ARM Coretex-A53 in 6U VPX form factor *20 ADC 14-bit @ 4 GSPS and 16 DAC 14-bit @ 12 GSPS *Low Latency ADC/DAC turn around *125GHz front end RF input/output Band-Width (BW) *Direct to RF from Base-Band, L-Band, S-Band, C-Band *64GB File System *2x 128MB Boot Flash *4GB of DDR-4 (32-bit) with ECC to the HPS *Three banks of 8GB of DDR-4 (64-bit wide) with ECC to the FPGA for total of 24GB *Health Management through dedicated Processor per VITA 46.11 Tier-2 support

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Warp FPGA IP

The Altera Warp FPGA IP core, part of the Video and Vision Processing (VVP) Suite, delivers a high-performance solution for applying geometric corrections and non-linear transformations to real-time video streams.

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Warping Engine IP Core

Memory -to memory or memory to stream Warping engine for projectors, fish-eye lense correction or Head Up Displays (HUDs).

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WILDSTAR 3AE1 3U OpenVPX FPGA Processor (WS3AE1)

WS3AE1 3U OpenVPX FPGA Processor is a SOSA™-aligned Direct RF solution that delivers high-performance processing and eight channels each of 64 Gsps ADC and DAC at a 10-bit resolution. It includes up to two Analog Interface Mezzanine Sites. These can be populated with Annapolis or 3rd party/customer-designed RF Cards for front-end personalization (e.g. pre-filtering or analog conditioning) for applications of interest.

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WILDSTAR SAF1 Small Form Factor Module (WSSAF1)

WSSAF1 Small Form Factor Module is a SWaP-optimized direct RF solution that delivers high-performance processing and four channels each of 64 Gsps ADC and DAC at a 10-bit resolution. It is designed to mate with modular RF and digital I/O cards and includes a development kit.

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WireGuard 10Gbps IP core (WireGuard10G IP)

WireGuard10G-IP core is a high-performance hardware implementation of the WireGuard VPN protocol, delivering full 10 Gbps line-rate encryption and decryption with no CPU load or external memory required. It performs the complete WireGuard cryptographic processing entirely in programmable logic for secure and efficient FPGA-based networking applications.

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XAUI PHY FPGA IP

The XAUI PHY IFPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Altera FPGA to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module. You can implement the XAUI PHY in hard silicon in Intel's 65 nm and 40 nm FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. In Intel 20 nm and beyond FPGA families, a XAUI PHY can be implemented in soft IP.

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XIP1113B: AES256-GCM IP core

Balanced speed AES256-GCM core implements the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM) with few Gpbs linerates.

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Showing 892-900 of 939 Offerings