Rapid Recompile is an optional step in the Quartus® Prime software compilation flow that accelerates build times by reusing synthesis and fitting results from previous compilations. When design blocks remain unchanged, the tool skips reprocessing them—minimizing timing variation and reducing total compile time after small HDL modifications.
Rapid Recompile supports functional ECO flows and enables faster iteration without impacting the performance of unchanged logic.
As of Quartus Prime software version 18.0, Rapid Recompile for Stratix® 10 FPGAs includes:
- SignalTap™ logic analyzer support
- Post-fit incremental route support for SignalTap™