tCAM IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

DesignGateway Co., Ltd.

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tCAM-IP is a high-performance, ultra-low-latency, and configurable Ternary Content-Addressable Memory IP, delivering deterministic search at 300 MSPS with a fixed latency of 7 clock cycles. It enables packet matching and filtering at up to 300 million packets per second over 40G/100G Ethernet. Ideal for applications such as packet filtering, intelligent switches/routers, deep packet inspection, and network security.

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Key Features

High-Speed Packet Filtering: Up to 400 MSPS @ 400MHz searching speed, 1,000,000 Search/MHz
Low Latency: Searching latency is constant at 7 clock cycles
Flexible UDP Packet Filtering
FPGA Integration
Customizable

Offering Brief

Device Family	Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® 10 SX SoC FPGA, Stratix® 10 GX FPGA
Offering Status	Production
Integrated Testbench	No
Evaluation License	No
Design Examples Available	Yes
Demo	Yes
Compliance	No
Latest Quartus Version Supported	23.1.0
Development Language	Encrypted VHDL